MT16VDDT12864AG-40BDB Micron Technology Inc, MT16VDDT12864AG-40BDB Datasheet - Page 5

• Manufacturer Part Number: MT16VDDT12864AG-40BDB
• Manufacturer: Micron Technology Inc

Specifications of MT16VDDT12864AG-40BDB

• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184UDIMM
• Device Core Size: 64b
• Organization: 128Mx64
• Total Density: 1GByte
• Chip Density: 512Mb
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 2.6V
• Operating Current: 1.6A
• Number Of Elements: 16
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / Rohs Status: Not Compliant

Table 7:
PDF: 09005aef80739fa5/Source:09005aef807397e5
DD16C64_128_256x64A.fm - Rev. E 8/08 EN
RAS#, CAS#, WE#
DQS0–DQS7
CKE0, CKE1
DQ0–DQ63
CK0, CK0#,
CK1, CK1#,
DM0–DM7
CK2, CK2#
V
BA0, BA1
SA0–SA2
Symbol
S0#, S1#
A0–A13
DD
V
V
SDA
DDSPD
SCL
V
NC
/V
REF
SS
DD
Q
Pin Descriptions
Supply
Supply
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
I/O
I/O
I/O
–
Description
Address inputs: Provide the row address for ACTIVE commands, and the column address
and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the
memory array in the respective device bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank
selected by BA0 and BA1) or all device banks (A10 HIGH). The address inputs also provide
the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode
register (mode register or extended mode register) is loaded during the LOAD MODE
REGISTER command. A0–A12 (512MB and1GB) and A0–A13 (2GB).
Bank address: BA0 and BA1 define the device bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied.
Clock: CK and CK# are differential clock inputs. All control, command, and address input
signals are sampled on the crossing of the positive edge of CK and the negative edge of
CK#. Output data (DQ and DQS) is referenced to the crossings of CK and CK#.
Clock enable: CKE enables (registered HIGH) and CKE disables (registered LOW) the
internal clock, input buffers, and output drivers.
Input data mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH, along with that input data, during a write access. DM is sampled on
both edges of DQS. Although the DM pins are input-only, the DM loading is designed to
match that of the DQ and DQS pins.
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Chip selects: S# enables (registered LOW) and disables (registered HIGH) the command
decoder.
Presence-detect address inputs: These pins are used to configure the SPD EEPROM
address range on the I
Serial clock for SPD EEPROM: SCL is used to synchronize the presence-detect data
transfer to and from the module.
Data input/output: Data bus.
Data strobe: Output with read data. Edge-aligned with read data. Input with write data.
Center-aligned with write data. Used to capture data.
Serial data: SDA is a bidirectional pin used to transfer addresses and data into and out of
the presence-detect portion of the module.
Power supply: +2.5V ±0.2V (-40B: +2.6V ±0.1V).
SPD EEPROM power supply: +2.3V to +3.6V.
SSTL_2 reference voltage (V
Ground.
No connect: These pins are not connected on the module.
512MB, 1GB, 2GB (x64, DR) 184-Pin DDR SDRAM UDIMM
2
C bus.
DD
5
/2).
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Pin Assignments and Descriptions
©2004 Micron Technology, Inc. All rights reserved