MT16VDDT12864AG-40BDB Micron Technology Inc, MT16VDDT12864AG-40BDB Datasheet - Page 12

• Manufacturer Part Number: MT16VDDT12864AG-40BDB
• Manufacturer: Micron Technology Inc

Specifications of MT16VDDT12864AG-40BDB

• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184UDIMM
• Device Core Size: 64b
• Organization: 128Mx64
• Total Density: 1GByte
• Chip Density: 512Mb
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 2.6V
• Operating Current: 1.6A
• Number Of Elements: 16
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / Rohs Status: Not Compliant

Table 12:
PDF: 09005aef80739fa5/Source:09005aef807397e5
DD16C64_128_256x64A.fm - Rev. E 8/08 EN
Parameter/Condition
Operating one bank active-precharge current:
t
cycle; Address and control inputs changing once every two clock cycles
Operating one bank active-read-precharge current: BL = 2;
t
inputs changing once per clock cycle
Precharge power-down standby current: All device banks idle;
Power-down mode;
Idle standby current: CS# = HIGH; All device banks idle;
t
changing once per clock cycle; V
Active power-down standby current: One device bank active;
Power-down mode;
Active standby current: CS# = HIGH; CKE = HIGH; One device bank
active;
changing twice per clock cycle; Address and other control inputs
changing once per clock cycle
Operating burst read current: BL = 2; Continuous burst reads;
One device bank active; Address and control inputs changing once per
clock cycle;
Operating burst write current: BL = 2; Continuous burst writes;
One device bank active; Address and control inputs changing once per
clock cycle;
per clock cycle
Auto refresh current
Self refresh current: CKE ≤ 0.2V
Operating bank interleave read current: Four device bank
interleaving reads (BL = 4) with auto precharge;
t
READ or WRITE commands
CK =
RC =
CK =
CK =
t
t
t
t
RC (MIN);
CK (MIN); DQ, DM, and DQS inputs changing once per clock
CK (MIN); CKE = HIGH; Address and other control inputs
CK (MIN); Address and control inputs change only during active
t
RC =
t
t
CK =
CK =
t
RAS (MAX);
I
Values are for the MT46V64M8 DDR SDRAM only and are computed from values specified in the
512Mb (64 Meg x 8) component data sheet
DD
t
CK =
t
t
CK (MIN); I
CK (MIN); DQ, DM, and DQS inputs changing twice
Specifications and Conditions – 1GB
Notes:
t
t
CK =
CK =
t
CK (MIN); I
t
t
t
CK =
CK (MIN); CKE = LOW
CK (MIN); CKE = LOW
1. Value calculated as one module rank in this operating condition; all other module ranks in
2. Value calculated reflects all module ranks in this operating condition.
OUT
IN
t
I
DD
CK (MIN); DQ, DM, and DQS inputs
= 0mA
= V
OUT
2P (CKE LOW) mode.
REF
= 0mA; Address and control
for DQ, DM, and DQS
512MB, 1GB, 2GB (x64, DR) 184-Pin DDR SDRAM UDIMM
t
RC =
t
t
REFC =
REFC = 7.8125µs
t
RC =
t
RC (MIN);
t
RC (MIN);
t
RFC (MIN)
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Symbol
I
I
I
I
I
I
I
DD
DD
DD
I
I
DD
DD
DD
I
I
I
DD
DD
DD
DD
DD
DD
4W
3N
5A
2P
3P
4R
2F
0
1
5
6
7
1
1
2
2
1
2
2
2
1
2
2
1
1,280
1,520
1,560
1,600
5,520
3,640
-40B
880
720
960
176
80
80
Electrical Specifications
1,080
1,320
1,360
1,440
4,640
3,280
-335
720
560
800
160
80
80
©2004 Micron Technology, Inc. All rights reserved
1,080
1,320
1,360
1,280
4,640
3,240
-262
720
560
800
160
80
80
-26A/
1,200
1,200
1,120
4,480
2,840
-265
960
640
480
720
160
80
80
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA