MT16HTF25664AY-800G1 Micron Technology Inc, MT16HTF25664AY-800G1 Datasheet - Page 20

• Manufacturer Part Number: MT16HTF25664AY-800G1
• Manufacturer: Micron Technology Inc

Specifications of MT16HTF25664AY-800G1

• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 240UDIMM
• Device Core Size: 64b
• Organization: 256Mx64
• Total Density: 2GByte
• Chip Density: 1Gb
• Access Time (max): 40ps
• Maximum Clock Rate: 800MHz
• Operating Supply Voltage (typ): 1.8V
• Number Of Elements: 16
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 240
• Mounting: Socket
• Lead Free Status / Rohs Status: Compliant

Table 15: DDR2 I
Values shown for MT47H256M8 DDR2 SDRAM only and are computed from values specified in the 2Gb (256 Meg x 8) com-
ponent data sheet
PDF: 09005aef80f09084
htf16c64_128_256x64ay.pdf - Rev. G 3/10 EN
Parameter
Operating one bank active-precharge current:
(I
Address bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
CL = CL (I
t
bus inputs are switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
is LOW; Other control and address bus inputs are stable; Data bus inputs are
floating
Precharge quiet standby current: All device banks idle;
is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus
inputs are floating
Precharge standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data
bus inputs are switching
Active power-down current: All device banks open;
t
are stable; Data bus inputs are floating
Active standby current: All device banks open;
MAX (I
Other control and address bus inputs are switching; Data bus inputs are switch-
ing
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (I
=
puts are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst
read, I
MAX (I
Address bus inputs are switching; Data bus inputs are switching
Burst refresh current:
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and ad-
dress bus inputs are floating; Data bus inputs are floating
RCD =
CK (I
DD
t
RP (I
),
DD
t
RAS =
OUT
DD
DD
DD
t
); CKE is LOW; Other control and address bus inputs
RCD (I
DD
),
),
); CKE is HIGH, S# is HIGH between valid commands; Address bus in-
= 0mA; BL = 4, CL = CL (I
t
t
), AL = 0;
RP =
RP =
t
RAS MIN (I
DD
); CKE is HIGH, S# is HIGH between valid commands; Address
t
t
RP (I
RP (I
DD
t
CK =
DD
DD
Specifications and Conditions – 4GB
DD
DD
t
); CKE is HIGH, S# is HIGH between valid commands;
); CKE is HIGH, S# is HIGH between valid commands;
CK =
), AL = 0;
); CKE is HIGH, S# is HIGH between valid commands;
t
CK (I
t
CK (I
DD
),
DD
DD
t
CK =
t
), AL = 0;
RC =
); REFRESH command at every
t
CK (I
t
RC (I
512MB, 1GB, 2GB, 4GB (x64, DR) 240-Pin DDR2 UDIMM
t
DD
CK =
DD
),
),
t
DD4W
CK =
t
t
t
RAS =
CK =
t
RAS =
t
CK (I
CK =
t
CK =
t
CK (I
t
DD
CK (I
t
OUT
t
CK =
t
t
RAS MAX (I
t
CK (I
RAS MIN (I
CK =
),
20
DD
t
= 0mA; BL = 4,
DD
RAS =
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
),
t
DD
CK (I
),
t
t
CK (I
); CKE is
RAS =
t
RC =
t
RFC (I
t
DD
RAS
DD
DD
DD
Micron Technology, Inc. reserves the right to change products or specifications without notice.
); CKE
t
),
t
),
); CKE
RC
RAS
DD
t
RP
)
Symbol
I
I
I
I
I
I
I
DD4W
I
I
DD2Q
DD2N
DD3N
I
I
DD2P
DD3P
DD4R
DD0
DD1
DD5
DD6
1
1
2
2
2
2
1
2
2
2
1
1216
1256
1416
4480
-667
856
128
880
960
640
160
880
128
© 2003 Micron Technology, Inc. All rights reserved.
I
DD
Specifications
-53E
1096
1256
4160
776
896
128
720
800
560
160
720
128
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA