MAX11043ATL+ Maxim Integrated Products, MAX11043ATL+ Datasheet - Page 20

• Manufacturer Part Number: MAX11043ATL+
• Description: IC ADC 16BIT W/DAC 40-TQFN-EP
• Manufacturer: Maxim Integrated Products
• Type: ADC, DACr

Specifications of MAX11043ATL+

• Resolution (bits): 16 b
• Sampling Rate (per Second): 9.6M
• Data Interface: Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Number Of Converters: 4
• Conversion Rate: 1600 KSPs
• Resolution: 16 bit
• Interface Type: SPI
• Voltage Reference: 2.5 V
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Power Dissipation: 2963 mW
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Input Voltage: 3.3 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
SCHAN_<4:1>: Automatic ADC result output for each
channel (A, B, C, and D).
1 = ADC channel data is output on DOUT each time a
new result is valid in the sequence, A, B, C, and D.
0 = ADC data is not presented automatically for this
channel (default).
When SCHAN_ = 1, the selected ADC channel data is
automatically presented on DOUT each time EOC
asserts low in the sequence A, B, C, and D with the
unselected channels omitted. The data transitions on
the rising edge of SCLK. Force CS low to initiate trans-
mission. CS can go high between results. The MSB of
the first selected ADC channel outputs immediately
Fine DAC Register (09h)
X<15:12>: Don’t-care bits.
DAC_<11:0>: Contains current fine DAC output value.
When using the DACSTEP input to change the DAC
DACSTEP Register (0Ah)
X<15:12>: Don’t-care bits.
DACSTEP11:DACSTEP0<11:0>: Provides the size of
the DAC step. The value is positive only and the
UP/DWN input is used to set the direction. The value in
Coarse DACH/DACL Register (0Bh)
DACH7:DACH0<15:8>: High coarse DAC value.
DACL7:DACL0<7:0>: Low coarse DAC value.
20
DACSTEP7
DACH7
DACL7
BIT 15
BIT 15
BIT 15
______________________________________________________________________________________
DAC7
BIT 7
BIT 7
BIT 7
X
X
DACSTEP6
DACH6
DACL6
BIT 14
BIT 14
BIT 14
DAC6
BIT 6
BIT 6
BIT 6
X
X
DACSTEP5
DACH5
DACL5
BIT 13
BIT 13
BIT 13
DAC5
BIT 5
BIT 5
BIT 5
X
X
DACSTEP4
DACH4
DACL4
BIT 12
BIT 12
BIT 12
DAC4
BIT 4
BIT 4
BIT 4
X
X
DACSTEP11
after the falling edge of EOC. EOC goes high after the
last bit of the selected channels clocks out or one clock
cycle before the next result is ready. Insufficient SCLK
pulses result in truncated data. Extra clock pulses give
an undefined output. In scan mode, keep DIN high or
write data to the MAX11043 as usual. In scan mode,
the MAX11043 ignores requests for data reads.
DECSEL<0>: Decimate select.
1 = decimate by 12.
0 = decimate by 24 (default).
Set DECSEL high to decimate the ADC result by 12,
doubling the number of samples. The SPI interface is
limited to 40Mbps.
value, this register updates to the new value on the
next rising edge of the system clock following the rising
edge of DACSTEP. The power-on default is 0.
the fine DAC register updates on the next rising edge
of the system clock following the rising edge of the
DACSTEP input. The power-on default is 0.
Coarse DAC sets high and low references for the fine
DAC. The power-on default is 0.
DACSTEP3
DACH3
DAC11
DACL3
BIT 11
BIT 11
BIT 11
DAC3
BIT 3
BIT 3
BIT 3
DACSTEP10
DACSTEP2
DACH2
DAC10
DACL2
BIT 10
BIT 10
BIT 10
DAC2
BIT 2
BIT 2
BIT 2
DACSTEP9
DACSTEP1
DACH1
DACL1
DAC9
DAC1
BIT 9
BIT 1
BIT 9
BIT 1
BIT 9
BIT 1
DACSTEP8
DACSTEP0
DACH0
DACL0
DAC8
DAC0
BIT 8
BIT 0
BIT 8
BIT 0
BIT 8
BIT 0