MAX11043ATL+ Maxim Integrated Products, MAX11043ATL+ Datasheet - Page 18

• Manufacturer Part Number: MAX11043ATL+
• Description: IC ADC 16BIT W/DAC 40-TQFN-EP
• Manufacturer: Maxim Integrated Products
• Type: ADC, DACr

Specifications of MAX11043ATL+

• Resolution (bits): 16 b
• Sampling Rate (per Second): 9.6M
• Data Interface: Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Number Of Converters: 4
• Conversion Rate: 1600 KSPs
• Resolution: 16 bit
• Interface Type: SPI
• Voltage Reference: 2.5 V
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Power Dissipation: 2963 mW
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Input Voltage: 3.3 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
Table 2. SPI Register Map
18
ADDRESS
______________________________________________________________________________________
0Ah
0Bh
0Ch
0Dh
1Ah
1Bh
1Ch
1Dh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Eh
1Fh
ADCA
ADCB
ADCC
ADCD
ADCAB
ADCCD
ADCABCD
Status
Configuration
DAC
DACSTEP
DACH/DACL
ConfigA
ConfigB
ConfigC
ConfigD
Reference/Delay
AGain
BGain
CGain
DGain
Filter coefficient address
Filter coefficient data out
Filter coefficient data in
Flash mode
Flash addr
Flash data in
Flash data out
Reserved
Reserved
Reserved
Reserved
REGISTER NAME
ADC channel A result register
ADC channel B result register
ADC channel C result register
ADC channel D result register
ADC channels A and B results register
ADC channels C and D results register
ADC channels A, B, C, and D results register
Status register
Configures the device
Fine DAC value
Step size for DAC increment/decrement function
High and low coarse DAC values
ADC channel A configuration
ADC channel B configuration
ADC channel C configuration
ADC channel D configuration
Sets the operation state of the reference and buffers
Channel A fine gain
Channel B fine gain
Channel C fine gain
Channel D fine gain
Selects the filter coefficient to read or write. This autoincrements
each time the coefficient data register is accessed.
Coefficient RAMs output data
Filter coefficient data
Flash mode selection register
Flash address register
Flash data in register
Flash data out register
FUNCTION
—
—
—
—
Register Map
16/24
16/24
16/24
16/24
32/48
32/48
64/96
BITS
8 + 8
16
16
16
16
16
16
16
16
16
16
16
16
32
32
16
16
16
—
—
—
—
8
8
8