AD7712AN Analog Devices Inc, AD7712AN Datasheet - Page 3
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AD7712AN
Manufacturer Part Number
AD7712AN
Description
IC ADC SIGNAL COND LC2MOS 24-DIP
Manufacturer
Analog Devices Inc
Datasheet
1.AD7712ARZ.pdf
(28 pages)
Specifications of AD7712AN
Data Interface
Serial
Rohs Status
RoHS non-compliant
Number Of Bits
24
Sampling Rate (per Second)
1.03k
Number Of Converters
1
Power Dissipation (max)
45mW
Voltage Supply Source
Analog and Digital, Dual ±
Operating Temperature
-40°C ~ 85°C
Mounting Type
Through Hole
Package / Case
24-DIP (0.300", 7.62mm)
Resolution (bits)
24bit
Sampling Rate
1.028kSPS
Input Channel Type
Differential
Supply Voltage Range - Digital
4.75V To 5.25V
Supply Current
4.5mA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD7712AN
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
AD7712ANZ
Manufacturer:
ALTERA
Quantity:
300
SPECIFICATIONS
Parameter
REFERENCE OUTPUT
V
LOGIC INPUTS
LOGIC OUTPUTS
TRANSDUCER BURNOUT
SYSTEM CALIBRATION
NOTES
13
14
15
16
17
REV. F
BIAS
The AD7712 is tested with the following V
with AV
Guaranteed by design, not production tested.
After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, then the device will
output all 0s.
These calibration and span limits apply provided the absolute voltage on the AIN1 analog inputs does not exceed AV
than V
The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.
Output Voltage
Initial Tolerance
Drift
Output Noise
Line Regulation (AV
Load Regulation
External Current
Input Voltage Range
V
Input Current
All Inputs except MCLK IN
MCLK IN Only
V
V
Floating State Leakage Current
Floating State Output Capacitance
Current
Initial Tolerance
Drift
AIN1
AIN2
BIAS
OL
OH
V
V
V
V
Positive Full-Scale Calibration Limit
Negative Full-Scale Calibration Limit
Offset Calibration Limit
Input Span
Positive Full-Scale Calibration Limit
Negative Full-Scale Calibration Limit
Offset Calibration Limit
Input Span
INPUT
, Output Low Voltage
, Output High Voltage
INL
INH
INL
INH
SS
Rejection
DD
, Input Low Voltage
, Input Low Voltage
– 30 mV.
, Input High Voltage
, Input High Voltage
= 5 V and V
13
15
15
DD
SS
)
= –5 V, V
16, 17
17
BIAS
14
= 0 V.
(continued)
BIAS
15
15
15
15
voltages. With AV
A, S Versions
2.5
± 1
20
30
1
1.5
1
AV
or AV
or AV
V
or V
or V
65 to 85
± 10
0.8
2.0
0.8
3.5
0.4
4.0
± 10
9
4.5
± 10
0.1
(1.05
–(1.05
–(1.05
0.8
(2.1
(4.2
–(4.2
–(4.2
3.2
(8.4
SS
DD
+ 0.85
SS
SS
DD
DD
V
V
– 0.85
+ 3
+ 2.1
V
V
V
REF
REF
V
V
V
REF
REF
REF
– 3.5
– 2.1
V
V
REF
REF
REF
DD
/GAIN
/GAIN
REF
REF
)/GAIN
)/GAIN
)/GAIN
)/GAIN
)/GAIN
)/GAIN
= 5 V and V
V
)/GAIN
)/GAIN
1
REF
V
REF
–3–
SS
Unit
V nom
% max
ppm/°C typ
µV typ
mV/V max
mV/mA max
mA max
V max
V max
V min
V min
dB typ
µA max
V max
V min
V max
V min
V max
V min
µA max
pF typ
µA nom
% typ
%/°C typ
V max
V max
V max
V min
V max
V max
V max
V max
V min
V max
= 0 V, V
BIAS
= 2.5 V; with AV
Conditions/Comments
pk-pk Noise; 0.1 Hz to 10 Hz Bandwidth
Maximum Load Current 1 mA
See V
Whichever Is Smaller: +5 V/–5 V or +10 V/0 V
Nominal AV
Whichever Is Smaller: +5 V/0 V Nominal AV
See V
Whichever Is Greater: +5 V/–5 V or +10 V/0 V
Nominal AV
Whichever Is Greater: +5 V/0 V Nominal AV
Increasing with Gain
I
I
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
SINK
SOURCE
= 1.6 mA
BIAS
BIAS
= 100 µA
Input Section
Input Section
DD
DD
DD
= 10 V and V
DD
/V
/V
+ 30 mV or does not go more negative
SS
SS
SS
= 0 V, V
BIAS
= 5 V and
AD7712
DD
DD
/V
/V
SS
SS