AD7686BRMZ Analog Devices Inc, AD7686BRMZ Datasheet - Page 5

• Manufacturer Part Number: AD7686BRMZ
• Description: IC ADC 16BIT 500KSPS 10-MSOP
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of AD7686BRMZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 16
• Sampling Rate (per Second): 500k
• Number Of Converters: 1
• Power Dissipation (max): 21.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP (0.118", 3.00mm Width)
• Resolution (bits): 16bit
• Input Channel Type: Pseudo Differential
• Supply Voltage Range - Analogue: 4.5V To 5.5V
• Supply Voltage Range - Digital: 1.8V To 5.8V, 2.3V To 5.8V
• Sampling Rate: 500kSPS
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7686CBZ - BOARD EVALUATION FOR AD7686
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TIMING SPECIFICATIONS
−40°C to +85°C, VDD = 4.5 V to 5.5 V, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.
See Figure 3 and Figure 4 for load conditions.
Table 4.
Parameter
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width ( CS Mode)
SCK Period (CS Mode)
SCK Period (Chain Mode)
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with Busy Indicator)
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
VIO Above 4.5 V
VIO Above 2.7 V
VIO Above 2.3 V
VIO Above 4.5 V
VIO Above 2.3 V
Figure 3. Load Circuit for Digital Interface Timing
TO SDO
50pF
C
L
500µA
500µA
I
I
OL
OH
1.4V
Rev. B | Page 5 of 28
30% VIO
1
2
2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.
0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
t
DELAY
Figure 4. Voltage Levels for Timing
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
2V OR VIO – 0.5V
0.8V OR 0.5V
CONV
ACQ
CYC
CNVH
SCK
SCK
SCKL
SCKH
HSDO
DSDO
EN
DIS
SSDICNV
HSDICNV
SSCKCNV
HSCKCNV
SSDISCK
HSDISCK
DSDOSDI
2
Min
0.5
400
2
10
15
17
18
19
20
7
7
5
15
0
5
5
3
4
1
70% VIO
Typ
t
DELAY
2V OR VIO – 0.5V
0.8V OR 0.5V
Max
1.6
14
16
17
15
18
22
15
26
15
25
AD7686
2
1
Unit
μs
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns