AD7686BRMZ Analog Devices Inc, AD7686BRMZ Datasheet - Page 17

• Manufacturer Part Number: AD7686BRMZ
• Description: IC ADC 16BIT 500KSPS 10-MSOP
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of AD7686BRMZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 16
• Sampling Rate (per Second): 500k
• Number Of Converters: 1
• Power Dissipation (max): 21.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP (0.118", 3.00mm Width)
• Resolution (bits): 16bit
• Input Channel Type: Pseudo Differential
• Supply Voltage Range - Analogue: 4.5V To 5.5V
• Supply Voltage Range - Digital: 1.8V To 5.8V, 2.3V To 5.8V
• Sampling Rate: 500kSPS
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7686CBZ - BOARD EVALUATION FOR AD7686
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

CS MODE 3-WIRE, NO BUSY INDICATOR
This mode is most often used when a single AD7686 is
connected to an SPI-compatible digital host. The connection
diagram is shown in Figure 33, and the corresponding timing is
provided in Figure 34.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. Once a conversion is initiated, it continues to
completion irrespective of the state of CNV. For instance, it
could be useful to bring CNV low to select other SPI devices,
such as analog multiplexers. However, CNV must be returned
high before the minimum conversion time and held high until
the maximum conversion time to avoid generating the busy
signal indicator. When the conversion is complete, the AD7686
enters the acquisition phase and powers down. When CNV
goes low, the MSB is output onto SDO. The remaining data bits
are then clocked by subsequent SCK falling edges.
ACQUISITION
SDI = 1
CNV
SCK
SDO
t
CNVH
CONVERSION
Figure 34. CS Mode 3-Wire, No Busy Indicator Serial Interface Timing (SDI High)
t
CONV
t
EN
D15
1
Rev. B | Page 17 of 28
t
HSDO
D14
2
t
CYC
ACQUISITION
D13
The data is valid on both SCK edges. Although the rising edge
can be used to capture the data, a digital host using the SCK
falling edge allows a faster reading rate provided it has an
acceptable hold time. After the 16th SCK falling edge, or when
CNV goes high, whichever occurs first, SDO returns to high
impedance.
t
3
ACQ
t
DSDO
t
VIO
SCKL
t
SCKH
14
SDI
Figure 33. CS Mode 3-Wire, No Busy Indicator
AD7686
t
SCK
CNV
SCK
15
Connection Diagram (SDI High)
D1
SDO
16
D0
t
DIS
CLK
CONVERT
DATA IN
DIGITAL HOST
AD7686