LTC2408CG#TR Linear Technology, LTC2408CG#TR Datasheet - Page 20

• Manufacturer Part Number: LTC2408CG#TR
• Description: IC ADC 24BIT 8CH MICROPWR 28SSOP
• Manufacturer: Linear Technology

Specifications of LTC2408CG#TR

• Number Of Bits: 24
• Sampling Rate (per Second): 7.5
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP (0.200", 5.30mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIONS
LTC2404/LTC2408
SCKCLK
state. The internal serial clock (SCK) generated by the ADC
is applied to the multiplexer clock input (CLK).
In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CSADC. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CSADC. An internal weak pull-up
resistor is active on the SCK pin during the falling edge of
CSADC; therefore, the internal serial clock timing mode is
automatically selected if SCK is not externally driven.
The serial data output pin (SDO) is Hi-Z as long as CSADC
is HIGH. At any time during the conversion cycle, CSADC
may be pulled LOW in order to monitor the state of the
converter. Once CSADC is pulled LOW, SCK goes LOW
and EOC is output to the SDO pin. EOC = 1 while a
conversion is in progress and EOC = 0 if the device is in the
sleep state.
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the sleep state and enter the data output
20
CSMUX
CSADC
SDO
D
IN
TEST EOC
t
EOCtest
DON’T CARE
Hi-Z
U
TEST EOC
INFORMATION
U
Hi-Z
W
BIT31
Figure 10. Internal Serial Clock Timing Diagram
BIT30
TO 1.12V
–0.12V
BIT29
SIG
U
TO V
2.7V TO 5.5V
0.1V
REF
REF
BIT28
CC
EXR
BIT27 BIT26
MSB
V
V
CH0
TO CH7
MUXOUT
ADCIN
GND
LTC2404/LTC2408
CC
REF
state if CSADC remains LOW. In order to prevent the
device from exiting the low power sleep state, CSADC
must be pulled HIGH before the first rising edge of SCK. In
the internal SCK timing mode, SCK goes HIGH and the
device begins outputting data at time t
falling edge of CSADC (if EOC = 0) or t
goes LOW (if CSADC is LOW during the falling edge of
EOC). The value of t
internal oscillator (F
by an external oscillator of frequency f
3.6/f
device remains in the sleep state. The conversion result is
held in the internal static shift register.
If CSADC remains LOW longer than t
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle begins on
this first rising edge of SCK and concludes after the 32nd
rising edge. Data is shifted out the SDO pin on each falling
edge of SCK. The internally generated serial clock is output
CSMUX
CSADC
EOSC
SDO
SCK
CLK
D
BIT4 BIT3 BIT2 BIT1
LSB
F
IN
O
. If CSADC is pulled HIGH before time t
SUB
LSB
EN
SUB
LSB
D2
V
SUB
LSB
EOCtest
CC
D1
0
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
= logic LOW or HIGH). If F
CS
SUB
LSB
BIT0
D0
is 23 s if the device is using its
10k
EOCtest
EOSC
Hi-Z
DON’T CARE
EOCtest
EOCtest
, then t
, the first rising
TEST EOC
EOCtest
O
after EOC
after the
EOCtest
is driven
24048 F10
, the
is