MAX19516ETM+ Maxim Integrated Products, MAX19516ETM+ Datasheet - Page 12

• Manufacturer Part Number: MAX19516ETM+
• Description: IC ADC 10BIT 100MSPS DUAL 48TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX19516ETM+

• Number Of Bits: 10
• Sampling Rate (per Second): 100M
• Data Interface: Serial, Parallel
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFN Exposed Pad
• Conversion Rate: 100 MSPs
• Resolution: 10 bit
• Interface Type: SPI
• Snr: 60.1 dB
• Voltage Reference: 1.25 V
• Supply Voltage (max): 3.5 V
• Supply Voltage (min): 1.7 V
• Maximum Power Dissipation: 3200 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Input Voltage: 1.8 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Dual-Channel, 10-Bit, 100Msps ADC
12
1, 12, 13, 48
17, 18
25, 36
PIN
______________________________________________________________________________________
10
11
14
15
16
19
20
21
22
23
24
26
27
28
29
30
31
32
33
34
35
37
38
39
2
3
4
5
6
7
8
9
DCLKB
NAME
REFIO
SHDN
DORB
OVDD
AVDD
SYNC
SPEN
CLK+
CMA
INA+
INB+
CMB
CLK-
GND
INA-
INB-
D0B
D1B
D2B
D3B
D4B
D5B
D6B
D7B
D8B
D9B
D0A
D1A
D2A
D3A
D4A
D5A
D6A
I.C.
Analog Supply Voltage. Bypass each AVDD input pair (1, 48) and (12, 13) to GND with 0.1µF.
Channel A Common-Mode Input-Voltage Reference
Channel A Positive Analog Input
Channel A Negative Analog Input
Active-Low SPI Enable. Drive high to enable parallel programming mode.
Reference Input/Output. To use internal reference, bypass to GND with a > 0.1µF capacitor. See
the Reference Input/Output (REFIO) section for external reference adjustment.
Active-High Power-Down. If SPEN is high (parallel programming mode), a register reset is initiated
on the falling edge of SHDN.
Internally Connected. Leave unconnected.
Channel B Positive Analog Input
Channel B Negative Analog Input
Channel B Common-Mode Input-Voltage Reference
Clock-Divider Mode Synchronization Input
Clock Positive Input
Clock Negative Input. If CLK- is connected to ground, CLK+ is a single-ended logic-level clock
input. Otherwise, CLK+/CLK- are self-biased differential clock inputs.
Ground. Connect all ground inputs and EP (exposed pad) together.
Channel B Data Over Range
Channel B Data Clock
Channel B Three-State Digital Output, Bit 0 (LSB)
Channel B Three-State Digital Output, Bit 1
Channel B Three-State Digital Output, Bit 2
Channel B Three-State Digital Output, Bit 3
Digital Supply Voltage. Bypass each OVDD input to GND with 0.1µF capacitor.
Channel B Three-State Digital Output, Bit 4
Channel B Three-State Digital Output, Bit 5
Channel B Three-State Digital Output, Bit 6
Channel B Three-State Digital Output, Bit 7
Channel B Three-State Digital Output, Bit 8
Channel B Three-State Digital Output, Bit 9 (MSB)
Channel A Three-State Digital Output, Bit 0 (LSB)
Channel A Three-State Digital Output, Bit 1
Channel A Three-State Digital Output, Bit 2
Channel A Three-State Digital Output, Bit 3
Channel A Three-State Digital Output, Bit 4
Channel A Three-State Digital Output, Bit 5
Channel A Three-State Digital Output, Bit 6
FUNCTION
Pin Description