AD7713ARZ Analog Devices Inc, AD7713ARZ Datasheet - Page 5

• Manufacturer Part Number: AD7713ARZ
• Description: IC ADC SIGNAL COND LC2MOS 24SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD7713ARZ

• Data Interface: Serial
• Number Of Bits: 24
• Sampling Rate (per Second): 205
• Number Of Converters: 1
• Power Dissipation (max): 5.5mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Resolution (bits): 24bit
• Input Channel Type: Differential, Single Ended
• Supply Voltage Range - Analogue: 5V To 10V
• Supply Voltage Range - Digital: 4.75V To 5.25V
• Supply: RoHS Compliant
• Package: 24SOIC W
• Resolution: 24 Bit
• Sampling Rate: 3.9 KSPS
• Architecture: Delta-Sigma
• Number Of Adcs: 1
• Number Of Analog Inputs: 1|2
• Digital Interface Type: Serial (3-Wire, 4-Wire)
• Input Type: Voltage
• Signal To Noise Ratio: 131 dB
• Polarity Of Input Voltage: Unipolar|Bipolar
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING CHARACTERISTICS
Parameter
f
t
t
t
t
t
Self-Clocking Mode
External-Clocking Mode
NOTES
1
2
3
4
5
6
7
REV. D
CLK IN
Guaranteed by design, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
See Figures 10 to 13.
CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7713 is not in standby mode. If no clock is present in this case, the device can
The AD7713 is production tested with f
Specified using 10% and 90% points on waveform of interest.
These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
CLK IN LO
CLK IN HI
r
f
1
draw higher current than specified and possibly become uncalibrated.
extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and, as such, are independent of external bus loading capacitances.
5
5
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
2
3
4
5
6
7
8
9
10
14
15
16
17
18
19
SCLK
20
21
22
23
26
27
28
30
32
33
34
35
36
24
25
29
31
6
6
6
6
7
7
3, 4
Limit at T
(A, S Versions)
400
2
0.4
0.4
50
50
1000
0
0
2
0
4
4
t
t
t
3
50
0
4
4
0
10
f
0
0
2
0
4
10
2
2
2
t
10
t
10
5
0
0
4
2
30
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
t
t
/2
/2 + 30
/2
/5
CLK IN
CLK IN
+ 10
+ 10
at 2 MHz. It is guaranteed by characterization to operate at 400 kHz.
/2
/2 + 50
MIN
+ 20
+20
+ 20
+ 20
– SCLK High
1, 2
, T
MAX
(DV
Input Logic 0 = 0 V, Logic 1 = DV
DD
= 5 V
5%; AV
Unit
kHz min
MHz max
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns nom
ns nom
ns min
ns min
ns max
ns min
ns min
ns min
MHz max
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns max
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
–5–
DD
= 5 V or 10 V
DD
, unless otherwise noted.)
Conditions/Comments
Master Clock Frequency: Crystal Oscillator or
Externally Supplied for Specified Performance
Master Clock Input Low Time; t
Master Clock Input High Time
Digital Output Rise Time; Typically 20 ns
Digital Output Fall Time; Typically 20 ns
SYNC Pulse Width
DRDY to RFS Setup Time
DRDY to RFS Hold Time
A0 to RFS Setup Time
A0 to RFS Hold Time
RFS Low to SCLK Falling Edge
Data Access Time (RFS Low to Data Valid)
SCLK Falling Edge to Data Valid Delay
SCLK High Pulse Width
SCLK Low Pulse Width
A0 to TFS Setup Time
A0 to TFS Hold Time
TFS to SCLK Falling Edge Delay Time
TFS to SCLK Falling Edge Hold Time
Data Valid to SCLK Setup Time
Data Valid to SCLK Hold Time
Serial Clock Input Frequency
DRDY to RFS Setup Time
DRDY to RFS Hold Time
A0 to RFS Setup Time
A0 to RFS Hold Time
Data Access Time (RFS Low to Data Valid)
SCLK Falling Edge to Data Valid Delay
SCLK High Pulse Width
SCLK Low Pulse Width
SCLK Falling Edge to DRDY High
SCLK to Data Valid Hold Time
RFS/TFS to SCLK Falling Edge Hold Time
RFS to Data Valid Hold Time
A0 to TFS Setup Time
A0 to TFS Hold Time
SCLK Falling Edge to TFS Hold Time
Data Valid to SCLK Setup Time
Data Valid to SCLK Hold Time
5%; AGND = DGND = 0 V; f
CLKIN
CLK IN
= 2 MHz;
= 1/f
AD7713
CLK IN