AD7713ARZ Analog Devices Inc, AD7713ARZ Datasheet - Page 19

• Manufacturer Part Number: AD7713ARZ
• Description: IC ADC SIGNAL COND LC2MOS 24SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD7713ARZ

• Data Interface: Serial
• Number Of Bits: 24
• Sampling Rate (per Second): 205
• Number Of Converters: 1
• Power Dissipation (max): 5.5mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Resolution (bits): 24bit
• Input Channel Type: Differential, Single Ended
• Supply Voltage Range - Analogue: 5V To 10V
• Supply Voltage Range - Digital: 4.75V To 5.25V
• Supply: RoHS Compliant
• Package: 24SOIC W
• Resolution: 24 Bit
• Sampling Rate: 3.9 KSPS
• Architecture: Delta-Sigma
• Number Of Adcs: 1
• Number Of Analog Inputs: 1|2
• Digital Interface Type: Serial (3-Wire, 4-Wire)
• Input Type: Voltage
• Signal To Noise Ratio: 131 dB
• Polarity Of Input Voltage: Unipolar|Bipolar
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

word in the output register. If a new data-word becomes avail-
able to the output register while data is being read from the
output register, DRDY will not indicate this and the new data-
word will be lost to the user. DRDY is not affected by reading
from the control register or the calibration registers.
Data can be accessed from the output data register only when
DRDY is low. If RFS goes low with DRDY high, no data trans-
fer will take place. DRDY does not have any effect on reading
data from the control register or from the calibration registers.
Figure 10 shows a timing diagram for reading from the AD7713
in the self-clocking mode. This read operation shows a read
from the AD7713’s output data register. A read from the con-
trol register or calibration registers is similar, but, in these cases,
the DRDY line is not related to the read function. Depending
on the output update rate, it can go low at any stage in the
control/calibration register read cycle without affecting the read
and its status should be ignored. A read operation from either
the control or calibration registers must always read 24 bits of
data from the respective register.
Figure 10 shows a read operation from the AD7713. For the
timing diagram shown, it is assumed that there is a pull-up
resistor on the SCLK output. With DRDY low, the RFS input
is brought low. RFS going low enables the serial clock of the
AD7713 and also places the MSB of the word on the serial data
line. All subsequent data bits are clocked out on a high-to-low
transition of the serial clock and are valid prior to the following
rising edge of this clock. The final active falling edge of SCLK
clocks out the LSB, and this LSB is valid prior to the final active
rising edge of SCLK. Coincident with the next falling edge of
SCLK, DRDY is reset high. DRDY going high turns off the
SCLK and the SDATA outputs, this means that the data hold
time for the LSB is slightly shorter than for all other bits.
REV. D
SDATA (O)
SDATA (I)
DRDY (O)
SCLK (O)
SCLK (O)
RFS (I)
TFS (I)
A0 (I)
A0 (I)
Figure 11. Self-Clocking Mode, Control/Calibration Register Write Operation
Figure 10. Self-Clocking Mode, Output Data Read Operation
t
2
t
t
4
14
t
t
6
16
t
7
t
18
MSB
MSB
–19–
t
t
8
19
Write Operation
Data can be written to either the control register or calibration
registers. In either case, the write operation is not affected by
the DRDY line, and the write operation does not have any
effect on the status of DRDY. A write operation to the control
register or the calibration register must always write 24 bits to
the respective register.
Figure 11 shows a write operation to the AD7713. A0 determines
whether a write operation transfers data to the control register
or to the calibration registers. This A0 signal must remain valid
for the duration of the serial write operation. The falling edge of
TFS enables the internally generated SCLK output. The serial
data to be loaded to the AD7713 must be valid on the rising
edge of this SCLK signal. Data is clocked into the AD7713 on
the rising edge of the SCLK signal, with the MSB transferred
first. On the last active high time of SCLK, the LSB is loaded to
the AD7713. Subsequent to the next falling edge of SCLK, the
SCLK output is turned off. (The timing diagram of Figure 11
assumes a pull-up resistor on the SCLK line.)
External Clocking Mode
The AD7713 is configured for its external clocking mode by
tying the MODE pin low. In this mode, SCLK of the AD7713
is configured as an input, and an external serial clock must be
provided to this SCLK pin. This external clocking mode is
designed for direct interface to systems which provide a serial
clock output which is synchronized to the serial data output,
including microcontrollers, such as the 80C51, 87C51,
68HC11, and 68HC05, and most digital signal processors.
Read Operation
As with the self-clocking mode, data can be read from either the
output register, the control register, or the calibration registers.
A0 determines whether the data read accesses data from the
control register or from the output/calibration registers. This A0
t
9
t
9
t
10
t
10
LSB
LSB
t
3
t
17
THREE-STATE
t
5
t
15
AD7713