AD7713ARZ Analog Devices Inc, AD7713ARZ Datasheet - Page 23

• Manufacturer Part Number: AD7713ARZ
• Description: IC ADC SIGNAL COND LC2MOS 24SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD7713ARZ

• Data Interface: Serial
• Number Of Bits: 24
• Sampling Rate (per Second): 205
• Number Of Converters: 1
• Power Dissipation (max): 5.5mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Resolution (bits): 24bit
• Input Channel Type: Differential, Single Ended
• Supply Voltage Range - Analogue: 5V To 10V
• Supply Voltage Range - Digital: 4.75V To 5.25V
• Supply: RoHS Compliant
• Package: 24SOIC W
• Resolution: 24 Bit
• Sampling Rate: 3.9 KSPS
• Architecture: Delta-Sigma
• Number Of Adcs: 1
• Number Of Analog Inputs: 1|2
• Digital Interface Type: Serial (3-Wire, 4-Wire)
• Input Type: Voltage
• Signal To Noise Ratio: 131 dB
• Polarity Of Input Voltage: Unipolar|Bipolar
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table V shows some typical 8XC51 code used for a single 24-bit
read from the output register of the AD7713. Table V shows
some typical code for a single write operation to the control
register of the AD7713. The 8XC51 outputs the LSB first in a
write operation while the AD7713 expects the MSB first, so the
data to be transmitted has to be rearranged before being written
to the output serial register. Similarly, the AD7713 outputs the
MSB first during a read operation while the 8XC51 expects the
LSB first. Therefore, the data which is read into the serial buffer
needs to be rearranged before the correct data-word from the
AD7713 is available in the accumulator.
MOV SCON,#00010001B;
WAIT:
READ:
POLL:
READ 1:
MOV A,SBUF;
RLC A;
MOV B.0,C;
END:
FIN:
REV. D
RLC A; MOV B.1,C; RLC A; MOV B.2,C;
RLC A; MOV B.3,C; RLC A; MOV B.4,C;
RLC A; MOV B.5,C; RLC A; MOV B.6,C;
RLC A; MOV B.7,C;
MOV A,B;
MOV @R0,A; Write Data to Memory
INC R0;
DEC R1
MOV A,R1
JZ END
JMP WAIT
SETB 90H
SJMP FIN
NOP;
MOV A,P1;
ANL A,R6;
JZ READ;
SJMP WAIT;
CLR 90H;
CLR 98H;
MOV IE,#00010000B;
SETB 90H;
SETB 91H;
SETB 93H;
MOV R1,#003H;
MOV R0,#030H;
MOV R6,#004H;
JB 98H, READ1
SJMP POLL
Table V. 8XC51 Code for Reading from the AD7713
Increment Memory Location
Decrement Byte Counter
Jump if Zero
Fetch Next Byte
Bring RFS High
Configure 8051 for MODE 0
Disable All Interrupts
Set P1.0, Used as RFS
Set P1.1, Used as TFS
Set P1.3, Used as A0
Sets Number of Bytes to Be Read
in A Read Operation
Start Address for Where Bytes
Will Be Loaded
Use P1.2 as DRDY
Read Port 1
Mask Out All Bits Except DRDY
If Zero Read
Otherwise Keep Polling
Bring RFS Low
Clear Receive Flag
Tests Receive Interrupt Flag
Read Buffer
Rearrange Data
Reverse Order of Bits
–23–
MOV SCON,#00000000B;
MOV IE,#10010000B;
MOV IP,#00010000B;
SETB 91H;
SETB 90H;
MOV R1,#003H;
MOV R0,#030H;
MOV A,#00H;
MOV SBUF,A;
WAIT:
JMP WAIT;
INT ROUTINE:
NOP;
MOV A,R1;
JZ FIN;
DEC R1;
MOV A,@R;
INC R0;
RLC A;
MOV B.0,C; RLC A; MOV B.1,C; RLC A;
MOV B.2,C; RLC A; MOV B.3,C; RLC A;
MOV B.4,C; RLC A; MOV B.5,C; RLC A;
MOV B.6,C; RLC A: MOV B.7,C; MOV A,B;
CLR 93H;
CLR 91H;
MOV SBUF,A;
RETI;
FIN:
SETB 91H;
SETB 93H;
RETI;
AD7713 to 68HC11 Interface
Figure 18 shows an interface between the AD7713 and the
68HC11 microcontroller. The AD7713 is configured for its exter-
nal clocking mode, while the SPI port is used on the 68HC11,
which is in its single chip mode. The DRDY line from the AD7713
is connected to the Port PC2 input of the 68HC11, so the DRDY
line is polled by the 68HC11. The DRDY line can be connected to
the IRQ input of the 68HC11 if an interrupt driven system is
preferred. The 68HC11 MOSI and MISO lines should be config-
ured for wired-OR operation. Depending on the interface
configuration, it may be necessary to provide bidirectional buffers
between the 68HC11 MOSI and MISO lines.
The 68HC11 is configured in the master mode with its CPOL
bit set to a Logic 0 and its CPHA bit set to a Logic 1.
Table VI. 8XC51 Code for Writing to the AD7713
Configure 8051 for MODE 0
Operation and Enable Serial
Reception
Enable Transmit Interrupt
Prioritize the Transmit Interrupt
Bring TFS High
Bring RFS High
Sets Number of Bytes to Be
Written in a Write Operation
Start Address in RAM for Bytes
Clear Accumulator
Initialize the Serial Port
Wait for Interrupt
Interrupt Subroutine
Load R1 to Accumulator
If Zero Jump to FIN
Decrement R1 Byte Counter
Move Byte into the Accumulator
Increment Address
Rearrange Data—From LSB
First to MSB First
Bring A0 Low
Bring TFS Low
Write to Serial Port
Return from Subroutine
Set TFS High
Set A0 High
Return from Interrupt Subroutine
AD7713