MAX1202BEAP+ Maxim Integrated Products, MAX1202BEAP+ Datasheet - Page 15

• Manufacturer Part Number: MAX1202BEAP+
• Description: IC ADC 12BIT 8CH 20-SSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1202BEAP+

• Number Of Bits: 12
• Sampling Rate (per Second): 133k
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 640mW
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP
• Number Of Adc Inputs: 8
• Architecture: SAR
• Conversion Rate: 133 KSPs
• Resolution: 12 bit
• Input Type: Voltage
• Interface Type: Serial
• Voltage Reference: Internal 4.096 V or External
• Supply Voltage (max): 5 V
• Maximum Power Dissipation: 640 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Input Voltage: 4.096 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

conversion is started. Pulling CS high prevents data from
being clocked into the MAX1202/MAX1203 and three-
states DOUT, but it does not adversely affect an internal
clock mode conversion already in progress. When
internal clock mode is selected, SSTRB does not go into
a high-impedance state when CS goes high.
Figure 10 shows SSTRB timing in internal clock mode.
Data can be shifted in and out of the MAX1202/MAX1203
at clock rates up to 2.0MHz, if t
CS’s falling edge does not start a conversion on the
MAX1202/MAX1203. The first logic high clocked into DIN
is interpreted as a start bit and defines the first bit of the
control byte. A conversion starts on SCLK’s falling edge
Figure 9. Internal Clock Mode Timing
Figure 10. Internal Clock Mode SSTRB Detailed Timing
SSTRB
SCLK
CS
SSTRB
ADC STATE
DOUT
SCLK
DIN
CS
START
______________________________________________________________________________________
1
SEL2 SEL1 SEL0
2
IDLE
PD0 CLOCK IN
3
ACQ
4
UNI/
BIP
t
CSH
5
5V, 8-Channel, Serial, 12-Bit ADCs
is kept above 1.5µs.
SGL/
(SCLK = 2MHz)
DIF
ACQUISITION
6
Data Framing
1.5µs
PD1
7
PD0
t
SSTRB
8
CONVERSION
10µs MAX
t
CONV
t
NOTE: KEEP SCLK LOW DURING CONVERSION FOR BEST NOISE PERFORMANCE.
CONV
with 3V Digital Interface
9
after the eighth bit of the control byte (the PD0 bit) is
clocked into DIN. The start bit is defined as one of the
following:
If a falling edge on CS forces a start bit before B5
becomes available, the current conversion is termi-
nated and a new one started. Thus, the fastest the
MAX1202/MAX1203 can run is 15 clocks/conversion.
MSB B10
B11
10
The first high bit clocked into DIN with CS low any-
time the converter is idle (e.g., after V
The first high bit clocked into DIN after bit 5 (B5) of a
conversion in progress appears at DOUT.
11
B9
12
18
t
SCK
B2
IDLE
19
B1
20
LSB
B0
21
or
FILLED WITH
ZEROS
22
t
CSS
23
24
DD
is applied).
15