LTC2408CG#PBF Linear Technology, LTC2408CG#PBF Datasheet - Page 21

• Manufacturer Part Number: LTC2408CG#PBF
• Description: IC A/D CONV 24BIT 8-CHAN 28-SSOP
• Manufacturer: Linear Technology

Specifications of LTC2408CG#PBF

• Number Of Bits: 24
• Sampling Rate (per Second): 7.5
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP (0.200", 5.30mm Width)
• Number Of Elements: 1
• Resolution: 24Bit
• Architecture: Delta-Sigma
• Sample Rate: 0.008KSPS
• Input Polarity: Unipolar
• Input Type: Voltage
• Rated Input Volt: 6.188V
• Differential Input: No
• Power Supply Requirement: Single
• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Differential Linearity Error: 1LSB(Typ)
• Integral Nonlinearity Error: 15ppm of Vref
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: SSOP
• Input Signal Type: Single-Ended
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIONS
to the SCK pin. This signal may be used to shift the
conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of the
conversion result on the 32nd rising edge of SCK. After the
32nd rising edge, SDO goes HIGH (EOC = 1), SCK stays
HIGH, and a new conversion starts.
While operating in the internal serial clock mode, the SCK
output of the ADC may be used as the multiplexer clock
(CLK). D
edge of CLK. As shown in Figure 10, the multiplexer
channel is selected by serial shifting a 4-bit word into the
D
bit which must be HIGH in order to program a channel. The
next three bits determine which channel is selected, see
Table 3. On the rising edge of CSADC (falling edge of
CSMUX), the new channel is selected and will be valid for
the next conversion. If D
output state, the previous channel selection remains valid.
SCKCLK
CSMUX
CSADC
IN
SDO
D
pin on the rising edge of CLK. The first bit is an enable
IN
TEST EOC
IN
is latched into the multiplexer on the rising
t
EOCtest
DON’T CARE
Hi-Z
U
Figure 11. Internal Serial Clock with Reduced Data Output Length Timing Diagram
TEST EOC
INFORMATION
IN
U
is held LOW during the data
Hi-Z
W
BIT31
BIT30
TO 1.12V
–0.12V
BIT29
SIG
U
TO V
2.7V TO 5.5V
0.1V
REF
REF
BIT28
CC
EXR
BIT27 BIT26
MSB
V
V
CH0
TO CH7
MUXOUT
ADCIN
GND
LTC2404/LTC2408
CC
REF
Typically, CSADC remains LOW during the data output
state. However, the data output state may be aborted by
pulling CSADC HIGH anytime between the first and 32nd
rising edge of SCK, see Figure 11. On the rising edge of
CSADC, the device aborts the data output state and
immediately initiates a new conversion. This is useful for
systems not requiring all 32 bits of output data, aborting
an invalid conversion cycle, or synchronizing the start of
a conversion. If CSADC is pulled HIGH while the con-
verter is driving SCK LOW, the internal pull-up is not
available to restore SCK to a logic HIGH state. This will
cause the device to exit the internal serial clock mode on
the next falling edge of CSADC. This can be avoided by
adding an external 10k pull-up resistor to the SCK pin or
by never pulling CSADC HIGH when SCK is LOW.
Whenever SCK is LOW, the LTC2404/LTC2408’s internal
pull-up at pin SCK is disabled. Normally, SCK is not
externally driven if the device is in the internal SCK timing
CSMUX
CSADC
SDO
SCK
CLK
BIT12 BIT11 BIT10 BIT9
D
F
IN
O
EN
D2
V
CC
D1
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
CS
LTC2404/LTC2408
BIT8
D0
10k
Hi-Z
DON’T CARE
TEST EOC
21
24048 F11