AD73322LARU Analog Devices Inc, AD73322LARU Datasheet - Page 38

• Manufacturer Part Number: AD73322LARU
• Description: IC ANALOG FRONT END DUAL 28TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD73322LARU

• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Number Of Channels: 4
• Power (watts): 73mW
• Voltage - Supply, Analog: 2.7 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 28-TSSOP

AD73322L
INITIALIZATION
Following reset, the AD73322L is in its default condition, which
ensures that the device is in control mode and must be
programmed or initialized from the DSP to start conversions.
Because communications between AD73322L and the DSP are
interrupt driven, it is usually not practical to embed the initial-
ization codes into the body of the initialization routine. It is
more practical to put the sequence of initialization codes in a
data (or program) memory buffer and to access this buffer with
a pointer that is updated on each interrupt. If a circular buffer is
used, it allows the interrupt routine to check when the circular
buffer pointer has wrapped around—at which point the
initialization sequence is complete.
In FSLB configurations, a single control word per codec per
sample period is sent to the AD73322L. In nonFSLB, it is
possible to initialize the device in a single sample period
provided the SCLK rate is programmed to a high rate. It is also
possible to use autobuffering, in which case an interrupt is
generated when the entire initialization sequence has been sent
to the AD73322L.
RUNNING THE AD73322L WITH ADCS OR DACS IN
POWER-DOWN
The programmability of the AD73322L allows the user flexi-
bility in choosing what sections of the AD73322L need to be
powered up. This allows better matching of the power con-
sumption and application requirements, because the AD73322L
offers two ADCs and two DACs in any combination. The
AD73322L always interfaces to the DSP in a standard way,
regardless of what ADC or DAC sections are enabled or
disabled. Therefore, the DSP expects to receive two ADC
samples per sample period and to transmit two DAC samples
per sample period. If a particular ADC is disabled (in power-
down) then its sample value is invalid. Likewise, a sample sent
to a DAC which is disabled has no effect.
There are two distinct phases of operation of the AD73322L:
initialization of the device via each codec section’s control
registers, and operation of the converter sections of each codec.
The initialization phase involves programming the control
registers of the AD73322L to ensure the required operating
characteristics such as sampling rate, serial clock rate, and I/O
gain. There are several ways in which the DSP can be
programmed to initialize the AD73322L. These range from
hard-coding a sequence of DSP SPORT Tx register writes with
constants used for the initialization words, to putting the
initialization sequence in a circular data buffer and using an
autobuffered transmit sequence.
Rev. A | Page 38 of 48
Hard-coding involves creating a sequence of writes to the DSP’s
SPORT Tx buffer, which are separated by loops or instructions
that idle and wait for the next Tx interrupt to occur, as shown in
the code that follows.
The circular buffer approach can be useful if a long initiali-
zation sequence is required. The list of initialization words is
put into the buffer in the required order:
The DSP program initializes pointers to the top of the buffer:
and puts the first entry in the DSP’s transmit buffer so that it is
available at the first SDOFS pulse:
The DSP’s transmit interrupt is enabled:
.VAR/DM/RAM/CIRC init_cmds[16]; {Codec init sequence}
.VAR/DM/RAM stat_flag;
.INIT init_cmds:
ax0 = b#1000100100000100;
tx0 = ax0;
idle; {wait for tx register to send current word}
i3 = ^init_cmds;
ax0 = dm(i3,m1);
tx0 = ax0;
imask = b#0001000000;
b # 1 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 ,
b # 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 ,
b # 1 0 0 0 1 0 1 0 1 1 1 1 1 0 0 1 ,
b # 1 0 0 0 0 0 1 0 1 1 1 1 1 0 0 1 ,
b # 1 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 ,
b # 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 ,
b # 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 ,
b # 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ,
b # 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 ,
b # 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 ,
b # 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 ,
b # 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 ,
b # 1 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 ,
b # 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 ,
b # 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 ,
b # 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 ;
13 = %init_cmds;