AD73322LARU Analog Devices Inc, AD73322LARU Datasheet - Page 19

• Manufacturer Part Number: AD73322LARU
• Description: IC ANALOG FRONT END DUAL 28TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD73322LARU

• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Number Of Channels: 4
• Power (watts): 73mW
• Voltage - Supply, Analog: 2.7 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 28-TSSOP

The SPORT block diagram shown in Figure 19 details the
blocks associated with Codecs 1 and 2, including the eight
control registers (A–H), external MCLK to internal DMCLK
divider, and serial clock divider. The divider rates are controlled
by the setting of Control Register B. The AD73322L features a
master clock divider that allows users the flexibility of dividing
externally available high frequency DSP or CPU clocks to
generate a lower frequency master clock internally in the codec,
which may be more suitable for either serial transfer or
sampling rate requirements. The master clock divider has five
divider options (÷1 default condition, ÷2, ÷3, ÷4, ÷5) that are
set by loading the master clock divider field in Register B with
the appropriate code (see ). Once the internal device master
clock (DMCLK) has been set using the master clock divider, the
sample rate and serial clock settings are derived from DMCLK.
The SPORT can work at four different serial clock (SCLK) rates
chosen from DMCLK, DMCLK/2, DMCLK/4, or DMCLK/8,
where DMCLK is the internal or device master clock resulting
from the external or pin master clock being divided by the
master clock divider.
SPORT REGISTER MAPS
There are two register banks for each codec in the AD73322L,
the control register bank and the data register bank. The control
register bank consists of eight read/write registers, each eight
bits wide. Table 16 shows the control register map for the
AD73322L. The first two control registers, CRA and CRB, are
reserved for controlling the SPORT. They hold settings for
parameters such as serial clock rate, internal master clock rate,
sample rate and device count. As both codecs are internally
cascaded, registers CRA and CRB on each codec must be
programmed with the same setting to ensure correct operation
(this is shown in the programming examples).
The other five registers, CRC through CRH, are used to hold
control settings for the ADC, DAC, reference, power control,
and gain tap sections of the device. It is not necessary for the
contents of CRC through CRH on each codec be similar.
Control registers are written to on the negative edge of SCLK.
The data register bank consists of two, 16-bit registers that are
the DAC and ADC registers.
MASTER CLOCK DIVIDER
The AD73322L features a programmable master clock divider
that allows the user to reduce an externally available master
clock, at pin MCLK, by a ratio of 1, 2, 3, 4, or 5 to produce an
internal master clock signal (DMCLK) that is used to calculate
the sampling and serial clock rates. The master clock divider is
programmable by setting CRB:4-6. Table 12 shows the division
ratio corresponding to the various bit settings. The default
divider ratio is divide-by-one.
Rev. A | Page 19 of 48
Table 12. DMCLK (Internal) Rate Divider Settings
MCD2
0
0
0
0
1
1
1
1
SERIAL CLOCK RATE DIVIDER
The AD73322L features a programmable serial clock divider
that allows users to match the serial clock (SCLK) rate of the
data to that of the DSP engine or host processor. The maximum
SCLK rate available is DMCLK, and the other available rates are
DMCLK/2, DMCLK/4, and DMCLK/8. The slowest rate
(DMCLK/8) is the default SCLK rate. The serial clock divider is
programmable by setting bits CRB:2–3. Table 13 shows the
serial clock rate corresponding to the various bit settings.
Table 13. SCLK Rate Divider Settings
SCD1
0
0
1
1
SAMPLE RATE DIVIDER
The AD73322L features a programmable sample rate divider
that allows users flexibility in matching the codec’s ADC and
DAC sample rates (decimation/interpolation rates) to the needs
of the DSP software. The maximum sample rate available is
DMCLK/256, which offers the lowest conversion group delay,
while the other available rates are DMCLK/512, DMCLK/1024,
and DMCLK/2048. The slowest rate (DMCLK/2048) is the
default sample rate. The sample rate divider is programmable by
setting bits CRB:0-1. Table 14 shows the sample rate
corresponding to the various bit settings.
Table 14. Sample Rate Divider Settings
DIR1
0
0
1
1
MCD1
0
0
1
1
0
0
1
1
DIR0
0
1
0
1
SCD0
0
1
0
1
MCD0
0
1
0
1
0
1
0
1
SCLK Rate
DMCLK/2048
DMCLK/1024
DMCLK/512
DMCLK/256
SCLK Rate
DMCLK/8
DMCLK/4
DMCLK/2
DMCLK
DMCLK Rate
MCLK
MCLK/2
MCLK/3
MCLK/4
MCLK/5
MCLK
MCLK
MCLK
AD73322L