AD73322LARU Analog Devices Inc, AD73322LARU Datasheet - Page 24

• Manufacturer Part Number: AD73322LARU
• Description: IC ANALOG FRONT END DUAL 28TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD73322LARU

• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Number Of Channels: 4
• Power (watts): 73mW
• Voltage - Supply, Analog: 2.7 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 28-TSSOP

AD73322L
OPERATION
RESETTING THE AD73322L
The RESET pin resets all the control registers. All registers are
reset to zero, indicating that the default SCLK rate (DMCLK/8)
and sample rate (DMCLK/2048) are at a minimum to ensure
that slow speed DSP engines can communicate effectively. As
well as resetting the control registers using the RESET pin, the
device can be reset using the RESET bit (CRA:7) in Control
Register A. Both hardware and software resets require four
DMCLK cycles. On reset, DATA/ PGM (CRA:0) is set to 0
(default condition) thus enabling program mode. The reset
conditions ensure that the device must be programmed to the
correct settings after power-up or reset. Following a reset, the
SDOFS is asserted 2048 DMCLK cycles after RESET going high.
The data that is output following reset and during program
mode is random and contains no valid information until either
data or mixed mode is set.
POWER MANAGEMENT
The individual functional blocks of the AD73322L can be
enabled separately by programming the Power Control Register
CRC. It allows certain sections to be powered down if not
required, which adds to the device’s flexibility in that the user
need not incur the penalty of having to provide power for a
certain section if it is not necessary to the design. The power
control registers provide individual control settings for the
major functional blocks on each codec unit and also a global
override that allows all sections to be powered up by setting the
bit. Using this method the user could, for example, individually
enable a certain section, such as the reference (CRC:5), and
disable all others. The global power-up (CRC:0) can be used to
enable all sections, but if power-down is required using the
global control, the reference is still enabled, in this case, because
its individual bit is set. Refer to Table 21 for details of the
settings of CRC.
NOTE: As both codec units share a common reference, the
reference control bits (CRC:5-7) in each SPORT are wire-OR’ e d
to allow either device to control the reference.
OPERATING MODES
There are three main modes of operation available on the
AD73322L: program, data, and mixed program/data modes.
Two other operating modes are typically reserved as diag-
nostic modes: digital and SPORT loop-back. The device
configuration—register settings—can be changed only in
program and mixed program/data modes. In all modes,
transfers of information to or from the device occur in 16-bit
packets; therefore the DSP engine’s SPORT is programmed for
16-bit transfers.
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PROGRAM (CONTROL) MODE
In program mode, CRA:0 = 0, the user writes to the control
registers to set up the device for desired operation—SPORT
operation, cascade length, power management, input/output
gain, etc. In this mode, the 16-bit information packet sent to the
device by the DSP engine is interpreted as a control word whose
format is shown in Table 17. In this mode, the user must
address the device to be programmed using the address field of
the control word. This field is read by the device and if it is zero
(000 bin), the device recognizes the word as being addressed to
it. If the address field is not zero, it is then decremented and the
control word is passed out of the device—either to the next
device in a cascade or back to the DSP engine.
This 3-bit address format allows the user to uniquely address
any one of up to eight devices in a cascade; please note that this
addressing scheme is valid only in sending control information
to the device —a different format is used to send DAC data to
the device(s). As the AD73322L is a dual codec, it features two
separate device addresses for programming purposes. If the
AD73322L is used in a standalone configuration connected to
a DSP, the two device addresses correspond to 0 and 1. If the
AD73322L is configured in a cascade of multiple, dual, or
single codecs (AD73322L or AD73311), its device addresses
correspond with its hardwired position in the cascade.
Following reset, when the SE pin is enabled, the codec responds
by raising the SDOFS pin to indicate that an output sample
event has occurred. Control words can be written to the device
to coincide with the data being sent out of the SPORT, as shown
in Figure 20, or they can lag the output words by a time interval
that should not exceed the sample interval. After reset, output
frame sync pulses occur at a slower default sample rate, which is
DMCLK/2048, until Control Register B is programmed, after
which the SDOFS pulses are set according to the contents of
DIR0-1. This allows slow controller devices to establish
communication with the AD73322L. During program mode,
the data output by the device is random and should not be
interpreted as ADC data.
SDOFS
SDIFS
SCLK
SDO
SDI
SE
Figure 20. Interface Signal Timing for Control Mode Operation
SAMPLE WORD (DEVICE 2)
CONTROL WORD
(DEVICE 2)
SAMPLE WORD (DEVICE 1)
CONTROL WORD
(DEVICE 1)