DS1386-8-120+ Maxim Integrated Products, DS1386-8-120+ Datasheet - Page 9

• Manufacturer Part Number: DS1386-8-120+
• Description: IC TIMEKEEPER RAM 64K 32-EDIP
• Manufacturer: Maxim Integrated Products
• Type: Clock/Calendar/NVSRAMr

Specifications of DS1386-8-120+

• Memory Size: 64K (8K x 8)
• Time Format: HH:MM:SS:hh (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 32-DIP Module (600 mil), 32-EDIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS1386/1386P
COMMAND REGISTER
Address location 0Bh is the Command Register where mask bits, control bits and flag bits reside. The
operation of each bit is as follows:
Bit 7: TE (Transfer Enable). This bit when set to a logic 0 will disable the transfer of data between
internal and external clock registers. The contents in the external clock registers are now frozen and reads
or writes will not be affected with updates. This bit must be set to a logic 1 to allow updates.
Bit 6: IPSW (Interrupt Switch). When set to a logic 1, INTA is the Time of Day Alarm and
INTB/(INTB) is the Watchdog Alarm. When set to logic 0, this bit reverses the output pins. INTA is now
the watchdog alarm output and INTB/(INTB) is the time of day alarm output.
Bit 5: IBH/LO (Interrupt B Sink or Source Current). When this bit is set to a logic 1 and V
is
CC
applied, INTB/(INTB) will source current (see DC characteristics IOH). When this bit is set to a logic 0,
INTB will sink current (see DC characteristics IOL).
Bit 4: PU/LVL (Interrupt Pulse Mode or Level Mode). This bit determines whether both interrupts
will output a pulse or level signal. When set to a logic 0, INTA and INTB/(INTB) will be in the level
mode. When this bit is set to a logic 1, the pulse mode is selected and INTA will sink current for a
minimum of 3ms and then release. INTB/(INTB) will either sink or source current, depending on the
condition of Bit 5, for a minimum of 3ms and then release. INTB will only source current when there is a
voltage present on V
.
CC
Bit 3: WAM (Watchdog Alarm Mask). When this bit is set to a logic 0, the watchdog interrupt output
will be activated. The activated state is determined by bits 1,4,5, and 6 of the Command Register. When
this bit is set to a logic 1, the watchdog interrupt output is deactivated.
Bit 2: TDM (Time-of-Day Alarm Mask). When this bit is set to a logic 0, the time of day alarm
interrupt output will be activated. The activated state is determined by bits 0,4,5, and 6 of the Command
Register. When this bit is set to a logic 1, the time of day alarm interrupt output is deactivated.
Bit 1: WAF (Watchdog Alarm Flag). This bit is set to a logic 1 when a watchdog alarm interrupt
occurs. This bit is read only. The bit is reset when any of the watchdog alarm registers are accessed.
When the interrupt is in the pulse mode (see bit 4 definition), this flag will be in the logic 1 state only
during the time the interrupt is active.
Bit 0: TDF (Time-of-Day Flag). This is a read-only bit. This bit is set to a logic 1 when a time of day
alarm has occurred. The time the alarm occurred can be determined by reading the time of day alarm
registers. This bit is reset to a logic 0 state when any of the time of day alarm registers are accessed.
When the interrupt is in the pulse mode (see bit 4 definition), this flag will be in the logic 1 state only
during the time the interrupt is active.
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