DS1386-8-120+ Maxim Integrated Products, DS1386-8-120+ Datasheet - Page 3

• Manufacturer Part Number: DS1386-8-120+
• Description: IC TIMEKEEPER RAM 64K 32-EDIP
• Manufacturer: Maxim Integrated Products
• Type: Clock/Calendar/NVSRAMr

Specifications of DS1386-8-120+

• Memory Size: 64K (8K x 8)
• Time Format: HH:MM:SS:hh (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 32-DIP Module (600 mil), 32-EDIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS1386/1386P
PACKAGES
The DS1386 is available in two packages (32-pin encapsulated DIP module and 34-pin PowerCap
module). The 32-pin DIP style module integrates the crystal, lithium energy source, and silicon all in one
package. The 34-pin PowerCap Module Board is designed with contacts for connection to a separate
PowerCap (DS9034PCX) that contains the crystal and battery. This design allows the PowerCap to be
mounted on top of the DS1386P after the completion of the surface mount process. Mounting the
PowerCap after the surface mount process prevents damage to the crystal and battery due to high
temperatures required for solder reflow. The PowerCap is keyed to prevent reverse insertion. The
PowerCap Module Board and PowerCap are ordered separately and shipped in separate containers. The
part number for the PowerCap is DS9034PCX.
OPERATION—READ REGISTERS
The DS1386 executes a read cycle whenever WE (Write Enable) is inactive (High), CE (Chip Enable)
and OE (Output Enable) are active (Low). The unique address specified by the address inputs (A0-A14)
defines which of the registers is to be accessed. Valid data will be available to the eight data output
drivers within t
(Access Time) after the last address-input signal is stable, providing that CE and OE
ACC
access times are also satisfied. If OE and CE access times are not satisfied, then data access must be
measured from the latter occurring signal (CE or OE) and the limiting parameter is either t
for CE or
CO
t
for OE rather than address access.
OE
OPERATION—WRITE REGISTERS
The DS1386 is in the write mode whenever the WE (Write Enable) and CE (Chip Enable) signals are in
the active (Low) state after the address inputs are stable. The latter occurring falling edge of CE or WE
will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE
or WE. All address inputs must be kept valid throughout the write cycle. WE must return to the high state
for a minimum recovery state (t
) before another cycle can be initiated. Data must be valid on the data
WR
bus with sufficient Data Set-Up (t
) and Data Hold Time (t
) with respect to the earlier rising edge of
DS
DH
CE or WE. The OE control signal should be kept inactive (High) during write cycles to avoid bus
contention. However, if the output bus has been enabled (CE and OE active), then WE will disable the
outputs in t
from its falling edge.
ODW
DATA RETENTION
The RAMified Timekeeper provides full functional capability when V
is greater than 4.5V and write-
CC
protects the register contents at 4.25V typical. Data is maintained in the absence of V
without any
CC
additional support circuitry. The DS1386 constantly monitors V
. Should the supply voltage decay, the
CC
RAMified Timekeeper will automatically write-protect itself and all inputs to the registers become “don’t
care.” The two interrupts INTA and INTB (INTB) and the internal clock and timers continue to run
regardless of the level of V
. However, it is important to insure that the pull-up resistors used with the
CC
interrupt pins are never pulled up to a value that is greater than V
+ 0.3V. As V
falls below
CC
CC
approximately 3.0V, a power-switching circuit turns the internal lithium energy source on to maintain the
clock and timer data and functionality. It is also required to insure that during this time (battery backup
mode), the voltage present at INTA and INTB (INTB) never exceeds 3.0V. During power-up, when V
CC
rises above approximately 3.0V, the power switching circuit connects external V
and disconnects the
CC
internal lithium energy source. Normal operation can resume after V
exceeds 4.5V for a period of
CC
200ms.
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