DP8570AN National Semiconductor, DP8570AN Datasheet - Page 16

• Manufacturer Part Number: DP8570AN
• Description: IC TIMER CLOCK PERIPHERAL 28 DIP
• Manufacturer: National Semiconductor
• Type: Timer Clock Peripheral (TCP)r

Specifications of DP8570AN

• Memory Size: 44B
• Time Format: HH:MM:SS:hh (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 28-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP8570AN

Functional Description
Note 1 PS Page Select (Bit D7 of Main Status Register)
Note 2 RS Register Select (Bit D6 of Main Status Register)
Note 3 The LSB counters count 0–99 until the hundreds of days counter
reaches 3 Then the LSB counters count to 65 or 66 (if a leap year) The
rollover is from 365 366 to 1
01 – 1F
A0-4
CONTROL REGISTERS
COUNTERS (CLOCK CALENDAR)
TIMER DATA REGISTERS
TIME COMPARE RAM
TIME SAVE RAM
0D
1D
00
01
02
03
04
01
02
03
04
05
06
07
08
09
0A
0B
0C
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1E
1F
(Note 1) (Note 2)
PS
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
TABLE VII Register Counter RAM
Addressing for DP8570A
RS
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
1
Main Status Register
Timer 0 Control Register
Timer 1 Control Register
Periodic Flag Register
Interrupt Routing Register
Real Time Mode Register
Output Mode Register
Interrupt Control Register 0
Interrupt Control Register 1
1 100 1 10 Seconds (0– 99)
Seconds
Minutes
Hours
Days of
Months
Years
Julian Date (LSB)
Julian Date
Day of Week
Timer 0 LSB
Timer 0 MSB
Timer 1 LSB
Timer 1 MSB
Sec Compare RAM
Min Compare RAM
Hours Compare
DOM Compare
Months Compare
DOW Compare RAM (1 – 7)
Seconds Time Save RAM
Minutes Time Save RAM
Hours Time Save RAM
Day of Month Time Save RAM
Months Time Save RAM
RAM
RAM Test Mode Register
2nd Page General Purpose RAM
Month
RAM
RAM
RAM
Description
(Continued)
(0– 59)
(0– 59)
(1– 12 0– 23)
(1– 12)
(0– 99)
(0– 99) (Note 3)
(0– 3)
(1– 7)
(0– 59)
(0– 59)
(1– 12 0 – 23)
(1– 12)
(1– 28 29 30 31)
(1– 28 29 30 31)
16
MAIN STATUS REGISTER
The Main Status Register is always located at address 0
regardless of the register block or the page selected
D0 This read only bit is a general interrupt status bit that is
taken directly from the interrupt pins The bit is a one when
an interrupt is pending on either the INTR pin or the MFO
pin (when configured as an interrupt) This is unlike D3– D5
which can be set by an internal event but may not cause an
interrupt This bit is reset when the interrupt status bits in the
Main Status Register are cleared
D1– D5 These five bits of the Main Status Register are the
main interrupt status bits Any bit may be a one when any of
the interrupts are pending Once an interrupt is asserted the
interrupt status bits are not reset when read Except for D1
to reset an interrupt a one is written back to the correspond-
ing bit that is being tested D1 is reset whenever the PFAIL
pin
reading the register in a polled mode D1 D3– D5 are set
regardless of whether these interrupts are masked or not by
bits D6 and D7 of Interrupt Control Registers 0 and 1
D6 and D7 These bits are Read Write bits that control
which register block or RAM page is to be selected Bit D6
controls the register block to be accessed (see memory
map) The memory map of the clock is further divided into
two memory pages One page is the registers clock and
timers and the second page contains 31 bytes of general
purpose RAM The page selection is determined by bit D7
P will read this register to determine the cause These
e
logic 1 This prevents loss of interrupt status when
TL F 8638– 14