DP8570AN National Semiconductor, DP8570AN Datasheet - Page 11

• Manufacturer Part Number: DP8570AN
• Description: IC TIMER CLOCK PERIPHERAL 28 DIP
• Manufacturer: National Semiconductor
• Type: Timer Clock Peripheral (TCP)r

Specifications of DP8570AN

• Memory Size: 44B
• Time Format: HH:MM:SS:hh (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 28-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP8570AN

Functional Description
The user may choose to have this power failed signal lock-
out the TCP’s data bus within 30
delay the lock-out to enable P access after power failure is
detected This delay is enabled by setting the delay enable
bit in the Routing Register Also if the lock-out delay was
not enabled the TCP will disconnect itself from the bus with-
in 30
power failure is detected a safety circuit will ensure that if a
read or write is held active continuously for greater than
30 s after the power fail signal is asserted the lock-out will
be forced If a lock-out delay is enabled the DP8570A will
remain active for 480
will enable the
fore total system collapse When the host CPU is finished
accessing the TCP it may force the bus lock-out before
480 s has elapsed by resetting the delay enable bit
The battery switch over circuitry is completely independent
of the PFAIL pin A separate circuit compares V
V
to operate from the V
voltage At this time the battery supply is switched in V
disconnected and the device is now in the standby mode If
indeterminate operation of the battery switch over circuit is
to be avoided then the voltage at the V
allowed to equal the voltage at the V
BB
voltage As the main supply fails the TCP will continue
s min
P to perform last minute bookkeeping be-
63
CC
s max If chip select is low when a
s after power fail is detected This
pin until V
FIGURE 6 System-Battery Switchover (Upper Left) Power Fail
s min 63
CC
BB
(Continued)
falls below the V
CC
pin
pin must not be
and Lock-Out Circuits (Lower Right)
s max or to
CC
to the
CC
BB
is
11
After the generation of a lock-out signal and eventual
switch in of the battery supply the pins of the TCP will be
configured as shown in Table II Outputs that have a pull-up
resistor should be connected to a voltage no greater than
V
The Timer and Interrupt Power Fail Operation bits in the
Real-Time Mode Register determine whether or not the tim-
ers and interrupts will continue to function after a power fail
event
As power returns to the system the battery switch over cir-
cuit will switch back to V
greater than the battery voltage The chip will remain in the
locked out state as long as PFAIL
BB
TCK G0 G1
CS RD WR
INTR MFO
Oscillator
TABLE II Pin Isolation during a Power Failure
A0– A4
D0– D7
PFAIL
Pin
T1
Locked Out
Locked Out
Locked Out
Not Isolated
Not Isolated
Not Isolated
Not Isolated
PFAIL
Logic 0
CC
power as soon as it becomes
e
e
0 When PFAIL
Standby Mode
Locked Out
Locked Out
Locked Out
Not Isolated
Locked Out
Not Isolated
Open Drain
V
BB l
TL F 8638 – 8
V
CC
e
1