DP8570AN National Semiconductor, DP8570AN Datasheet - Page 14

• Manufacturer Part Number: DP8570AN
• Description: IC TIMER CLOCK PERIPHERAL 28 DIP
• Manufacturer: National Semiconductor
• Type: Timer Clock Peripheral (TCP)r

Specifications of DP8570AN

• Memory Size: 44B
• Time Format: HH:MM:SS:hh (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 28-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP8570AN

Functional Description
of the input data registers are loaded into the timer The
output will stay high until the counter reaches zero At zero
the output is reset The result is an output pulse whose du-
ration is equal to the input clock period times the count
value (N) loaded into the input data register This is shown
in Figure 8
Pulse Width
An interrupt is generated when the zero count is reached
This can be used for one-time interrupts that are set to oc-
cur a certain amount of time in the future In this mode the
Timer Start Stop bit (TSS) is automatically reset upon zero
detection This removes the need to reset TSS before start-
ing another operation
The count down operation may be temporarily suspended
either under software control by setting the Count Hold
Gate bit in the timer register high or in hardware by setting
the G0 or G1 pin high
The above discussion assumes that the timer outputs were
programmed to be non-inverting outputs (active high) If the
polarity of the output waveform is wrong for the application
the polarity can be reversed by configuring the Output Mode
Register The drive configuration can also be programmed
to be push pull or open drain
MODE 1 RATE GENERATOR
When operating in this mode the timer will operate continu-
ously Before the timer is started its output is low When the
timer is started the input data register contents are loaded
into the counter on the negative clock edge and the output
is set high (again assuming the Output Mode Register is
programmed active high) The timer will then count down to
zero Once the zero count is reached the output goes low
e
Clock Period
c
N
FIGURE 8 Typical Waveforms for Timer Mode 0
FIGURE 9 Timing Waveforms for Timer Mode 1
(Continued)
(Timer Output Programmed Active High)
(Timer Output Programmed Active High)
14
for one clock period of the timer clock Then on the next
clock the counter is reloaded automatically and the count-
down repeats itself The output shown in Figure 9 is a
waveform whose pulse width and period is determined by N
the input register value and the input clock period
Period
Pulse Width
The G0 or G1 pin and the count hold gate bit can be used
to suspend the appropriate timer countdown when either is
high Again the output polarity is controllable as in mode 0
If enabled an interrupt is generated whenever the zero
count is reached This can be used to generate a periodic
interrupt
MODE 2 SQUARE WAVE GENERATOR
This mode is also cyclic but in this case a square wave
rather than a pulse is generated The output square wave
period is determined by the value loaded into the timer input
register This period and the duty cycle are
Period
When the timer is stopped the output will be low and when
the Start Stop bit is set high the timer’s counter will be load-
ed on the next clock falling transition and the output will be
set high
The output will be toggled after the zero count is detected
and the counter will then be reloaded and the cycle will
continue Thus every N
as shown in Figure 10 Like the other modes the timer oper-
ation can be suspended either by software setting the count
hold gate bit (CHG) in the Timer Control Register or by us-
ing the gate pins An interrupt will be generated every falling
edge of the timer output if enabled
e
e
2(N
(N
e
a
a
Clock Period
1) (Clock Period)
1) (Clock Period)
a
1 counts the output gets toggled
TL F 8638– 10
TL F 8638 – 11
Duty Cycle
e
0 5