PCF8593P,112 NXP Semiconductors, PCF8593P,112 Datasheet

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PCF8593 Low power clock and calendar Rev. 04 — 6 October 2010 1. General description The PCF8593 is a CMOS consumption. Addresses and data are transferred serially via the two-line bidirectional 2 I C-bus. The built-in word address register is ...

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... NXP Semiconductors 4. Marking Table 2. Type number PCF8593P PCF8593T 5. Block diagram OSCI OSCO INT RESET SCL SDA Fig 1. PCF8593 Product data sheet Marking codes V DD OSCILLATOR RESET 2 I C-BUS INTERFACE V SS Block diagram of PCF8593 All information provided in this document is subject to legal disclaimers. ...

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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. Fig 3. 6.2 Pin description Table 3. Symbol OSCI OSCO RESET V SS SDA SCL INT V DD PCF8593 Product data sheet OSCI 1 2 OSCO RESET Top view. For mechanical details, see Pin configuration for DIP8 (PCF8593P) OSCI ...

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... NXP Semiconductors 7. Functional description The PCF8593 contains sixteen 8 bit registers with an 8 bit auto-incrementing address register, an on-chip 32.768 kHz oscillator circuit, a frequency divider and a serial two-line bidirectional I The first 8 registers (memory addresses 00h to 07h) are designed as addressable 8 bit parallel registers. The first register (memory address 00h) is used as a control and status register ...

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... NXP Semiconductors 7.3 Control and status register The control and status register is defined as the memory location 00h with free access for reading and writing via the I contents of the control and status register (see Fig 4. PCF8593 Product data sheet 2 C-bus. All functions and options are controlled by the ...

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... NXP Semiconductors 7.4 Counter registers The format for 24 hour or 12 hour clock modes can be selected by setting the most significant bit of the hours counter register. The format of the hours counter is shown in Figure 5. MSB 7 013aaa383 Fig 5. The year and date are stored in memory location 05h (see months are in memory location 06h (see Fig 6 ...

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... NXP Semiconductors In the event-counter mode, events are stored in BCD format the most significant and D0 the least significant digit. The divider is by-passed. In the different modes the counter registers are programmed and arranged as shown in Figure 8. Counter cycles are listed in Fig 8. PCF8593 Product data sheet ...

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... NXP Semiconductors Table 4. Unit hundredths of a second seconds minutes hours (24) hours (12) date months year weekdays timer 7.5 Alarm control register When the alarm enable bit of the control and status register is set (address 00h, bit 2) the alarm control register (address 08h) is activated. All alarm, timer, and interrupt output ...

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... NXP Semiconductors Fig 9. 7.6 Alarm registers All alarm registers are allocated with a constant address offset of 08h to the corresponding counter registers (see An alarm signal is generated when the contents of the alarm registers match bit-by-bit the contents of the involved counter registers. The year and weekday bits are ignored in a dated alarm ...

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... NXP Semiconductors Fig 10. Selection of alarm weekdays 7.7 Timer The timer (location 07h) is enabled by setting the control and status register to XX0X X1XX. The timer counts up from 0 (or a programmed value) to 99. On overflow, the timer resets to 0. The timer flag (LSB of control and status register) is set on overflow of the timer ...

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... NXP Semiconductors CONTROL/STATUS REGISTER (1) (1) If the alarm enable bit of the control and status register is reset (logic 0 signal is observed on the interrupt pin INT. Fig 11. Alarm and timer interrupt logic diagram 7.8 Event counter mode Event counter mode is selected by bits 4 and 5 which are logic 10 in the control and status register ...

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... NXP Semiconductors this mode, the timer (location 07h) increments once for every one, one hundred, ten thousand million events, depending on the value programmed in bits 0, 1 and 2 of the alarm control register. In all other events, the timer functions are as in the clock mode. ...

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... NXP Semiconductors In the 50 Hz clock mode or event-counter mode the oscillator is disabled and the oscillator input is switched to a high-impedance state. This allows the user to feed the 50 Hz reference frequency or an external high speed event signal into the input OSCI. 7.10.1 Designing When designing the printed-circuit board layout, keep the oscillator components as close to the IC package as possible, and keep all other signal lines as far away as possible ...

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... NXP Semiconductors 8. Characteristics of the I 8.1 Characteristics 2 The I C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial DAta line (SDA) and a Serial Clock Line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer is initiated only when the bus is not busy ...

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... NXP Semiconductors SDA SCL MASTER TRANSMITTER RECEIVER Fig 16. System configuration 8.1.4 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge cycle. • A slave receiver, which is addressed, must generate an acknowledge after the reception of each byte. • ...

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... NXP Semiconductors 2 8.2 I C-bus protocol 8.2.1 Addressing Before any data is transmitted on the I addressed first. The addressing is always carried out with the first byte transmitted after the start procedure. The clock and calendar acts as a slave receiver or slave transmitter. The clock signal SCL is only an input signal but the data signal SDA is a bidirectional line ...

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... NXP Semiconductors acknowledgement from slave SLAVE ADDRESS R/W (1) At this moment master transmitter becomes master receiver and PCF8593 slave receiver becomes slave transmitter. Fig 19. Master reads after setting word address (write word address; READ data) Fig 20. Master reads slave immediately after first byte (READ mode) ...

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... NXP Semiconductors 9. Limiting values Table 6. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol tot ESD stg T amb [1] Pass level; Human Body Model (HBM), according to [2] Pass level; Machine Model (MM), according to [3] Pass level; latch-up testing according to [4] According to the NXP store and transport requirements (see stored at a temperature of +8 ° ...

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... NXP Semiconductors 10. Characteristics 10.1 Static characteristics Table 7. Static characteristics Symbol Parameter V supply voltage DD I supply current DD Pin SDA, SCL and INT V LOW-level input voltage IL V HIGH-level input voltage IH I LOW-level output current OL I input leakage current LI C input capacitance I Pins OSCI and RESET ...

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... NXP Semiconductors Fig 21. Typical supply current in clock mode as a function of supply voltage PCF8593 Product data sheet (μ ° kHz; T SCL amb All information provided in this document is subject to legal disclaimers. Rev. 04 — 6 October 2010 PCF8593 Low power clock and calendar 001aam493 (V) DD © ...

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... NXP Semiconductors 10.2 Dynamic characteristics Table 8. Dynamic characteristics Symbol Parameter Oscillator C capacitance on pin OSCO OSCO Δf /f relative oscillator frequency osc osc variation f external clock frequency clk(ext) Quartz crystal parameters (f = 32.768 kHz) R series resistance S C parallel load capacitance L C trimmer capacitance ...

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... NXP Semiconductors START PROTOCOL CONDITION (S) t SU;STA SCL t BUF SDA t HD;STA 2 Fig 22. I C-bus timing diagram; rise and fall times refer to V PCF8593 Product data sheet BIT 7 BIT 6 MSB (A6) (A7 LOW HIGH SCL SU;DAT HD;DAT IL All information provided in this document is subject to legal disclaimers. ...

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... NXP Semiconductors 11. Application information 11.1 Oscillator frequency adjustment 11.1.1 Method 1: Fixed OSCI capacitor By evaluating the average capacitance necessary for the application layout a fixed capacitor can be used. The frequency is best measured via the 1 Hz signal which can be programmed to occur at the interrupt output (pin 7). The frequency tolerance depends on the quartz crystal tolerance, the capacitor tolerance and the device-to-device tolerance (on average ± ...

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... NXP Semiconductors Fig 23. Application example PCF8593 Product data sheet RESET CLOCK/CALENDAR OSCI PCF8593 OSCO V SS All information provided in this document is subject to legal disclaimers. Rev. 04 — 6 October 2010 PCF8593 Low power clock and calendar RESET RESET SDA MASTER TRANSMITTER/ RECEIVER SCL V SS ...

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... NXP Semiconductors 12. Package outline DIP8: plastic dual in-line package; 8 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

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... NXP Semiconductors SO8: plastic small outline package; 8 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

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... NXP Semiconductors 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...

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... NXP Semiconductors 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...

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... NXP Semiconductors Fig 26. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. PCF8593 Product data sheet maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature MSL: Moisture Sensitivity Level All information provided in this document is subject to legal disclaimers ...

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... NXP Semiconductors 14. Abbreviations Table 11. Acronym AM BCD CMOS ESD HBM LSB MM MSB MSL MUX PCB PM POR PPM RF RAM SCL SDA SMD PCF8593 Product data sheet Abbreviations Description Ante Meridiem Binary Coded Decimal Complementary Metal-Oxide Semiconductor ElectroStatic Discharge Human Body Model Inter-Integrated Circuit bus ...

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... NXP Semiconductors 15. References [1] AN10365 — Surface mount reflow soldering description [2] IEC 60134 — Rating systems for electronic tubes and valves and analogous semiconductor devices [3] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena [4] IPC/JEDEC J-STD-020 — Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices [5] JESD22-A114 — ...

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... Document ID Release date PCF8593 v.4 20101006 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. PCF8593_3 19970325 PCF8593_2 19940829 PCF8593_1 ...

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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

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... For sales office addresses, please send an email to: PCF8593 Product data sheet own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...

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... NXP Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 4 7.1 Counter function modes . . . . . . . . . . . . . . . . . . 4 7.2 Alarm function modes . . . . . . . . . . . . . . . . . . . . 4 7.3 Control and status register . . . . . . . . . . . . . . . . 5 7 ...