pcf8593 NXP Semiconductors, pcf8593 Datasheet
pcf8593
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pcf8593 Summary of contents
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... DATA SHEET PCF8593 Low power clock/calendar Product specification Supersedes data of July 1994 File under Integrated Circuits, IC12 INTEGRATED CIRCUITS 1997 Mar 25 ...
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... Method 1: Fixed OSCI capacitor 14.1.2 Method 2: OSCI Trimmer 14.1.3 Method 3: direct output 15 PACKAGE OUTLINES 16 SOLDERING 16.1 Introduction 16.2 DIP 16.2.1 Soldering by dipping or by wave 16.2.2 Repairing soldered joints 16.3 SO 16.3.1 Reflow soldering 16.3.2 Wave soldering 16.3.3 Repairing soldered joints 17 DEFINITIONS 18 LIFE SUPPORT APPLICATIONS 2 C-BUS 19 PURCHASE OF PHILIPS I 2 Product specification PCF8593 2 C COMPONENTS ...
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... PCF8593T SO8 plastic small outline package; 8 leads; body width 3.9 mm 1997 Mar 25 2 The PCF8593 is a CMOS clock/calendar circuit, optimized = 0 to +70 C): for low power consumption. Addresses and data are amb transferred serially via the two-line bidirectional I The built-in word address register is incremented automatically after each written or read data byte ...
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... REGISTER 4 Fig.1 Block diagram. 4 100 Hz control/status 00 hundredths of a second 01 seconds minutes hours year/date weekdays/months timer 07 alarm control 08 alarm registers or RAM 0F MBD808 OSCI 1 2 OSCO PCF8593P PCF8593T 3 RESET MBD809 Fig.2 Pin configuration. Product specification PCF8593 INT 6 SCL 5 SDA ...
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... Philips Semiconductors Low power clock/calendar 7 FUNCTIONAL DESCRIPTION The PCF8593 contains sixteen 8-bit registers with an 8-bit auto-incrementing address register, an on-chip 32.768 kHz oscillator circuit, a frequency divider and a 2 serial two-line bidirectional I C-bus interface. The first 8 registers (memory addresses 00 to 07) are designed as addressable 8-bit parallel registers. The first register (memory address 00) is used as a control/status register ...
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... Hz 10 event-counter mode 11 test modes hold last count flag : 0 count 1 store and hold last count in capture latches stop counting flag : 0 count pulses 1 stop counting, reset divider Product specification PCF8593 ...
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... CLOCK MODES Fig.4 Register arrangement. 7 control/status free 04 free 05 free 06 timer alarm control 08 alarm alarm free 0C free 0D free 0E alarm timer 0F EVENT COUNTER MBD811 Product specification PCF8593 ...
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... BCD ten days ( binary) year ( binary, read the mask flag is set) memory location 06 (weekdays/months) unit months BCD ten months weekdays ( binary, read the mask flag is set) Product specification PCF8593 ...
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... Fig.9). Remark: in the 12 h mode, bits 6 and 7 of the alarm hours register must be the same as the hours counter. 9 Product specification PCF8593 CONTENTS OF THE MONTH COUNTER and and 11 2, year = 0 ...
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... PCF8593 ...
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... Product specification memory location 0E (alarm weekday/month) weekday 0 enabled when set weekday 1 enabled when set weekday 2 enabled when set weekday 3 enabled when set weekday 4 enabled when set weekday 5 enabled when set weekday 6 enabled when set not used Event counter mode PCF8593 ...
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... Product specification PCF8593 ...
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... CLOCK/CALENDAR ALARM alarm timer control alarm (1) alarm interrupt Fig.11 Alarm and timer interrupt logic diagram. 13 oscillator TIMER timer overflow control ALARM CONTROL REGISTER timer overflow INT interrupt MBD818 Product specification PCF8593 0 ...
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... It is recommended to set the stop counting flag of the control/status register before loading the actual time into the counters. Loading of illegal states may lead to a temporary clock malfunction. 14 Product specification PCF8593 PCF8593 MBD819 , an external 0.2 F. Note that the application, as their ...
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... HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P). SDA SCL START condition 1997 Mar 25 2 C-BUS data line change stable; of data allowed data valid Fig.13 Bit transfer. S Fig.14 Definition of start and stop conditions. 15 Product specification PCF8593 MBC621 SDA SCL P STOP condition MBC622 ...
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... In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition START CONDITION Fig.16 Acknowledgment on the I 16 Product specification PCF8593 MASTER MASTER TRANSMITTER / TRANSMITTER RECEIVER MBA605 not acknowledge acknowledge 8 9 clock pulse for ...
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... SDA is a bidirectional line. The clock/calendar slave address is shown in Fig.17. 9.2 Clock/calendar READ/WRITE cycles 2 The I C-bus configuration for the different PCF8593 READ and WRITE cycles is shown in Figs 18, 19 and 20. handbook, full pagewidth S SLAVE ADDRESS Fig.18 Master transmits to slave receiver (WRITE) mode. ...
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... Fig.20 Master reads slave immediately after first byte (READ mode). 1997 Mar 25 acknowledgement from slave SLAVE ADDRESS WORD ADDRESS this moment master - transmitter becomes master - receiver and PCF8593 slave - receiver becomes slave - transmitter acknowledgement acknowledgement from slave from slave 1 A DATA R/W n bytes auto increment ...
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... 0 MIN. 0 300 50 40 +85 65 +150 (1) MIN. TYP. 2.5 1.0 1.0 1.2 SS 1.0 4 Product specification PCF8593 MAX. UNIT 0 MAX. UNIT 6.0 V 6.0 V 6.0 V 6.0 V 200 ...
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... amb must exceed the specified minimum value by 300 mV to guarantee correct DDO ( (1) MIN. TYP. 250 MBD826 (V) Product specification PCF8593 MAX. UNIT 7 pF +250 ...
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... C; V amb DD note C-bus specification, with applications, is given in brochure “The I 21 MIN. TYP 1 4.7 4.7 4.0 4.7 4.0 250 0 4.0 Product specification PCF8593 MAX. UNIT MHz 100 kHz 100 1 ...
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... SDA t HD;STA Fig.22 I 1997 Mar 25 BIT 7 BIT 6 MSB (A6) (A7) t LOW t HIGH SCL SU;DAT t HD;DAT 2 C-bus timing diagram; rise and fall times refer Product specification PCF8593 BIT 0 ACKNOWLEDGE STOP LSB (A) CONDITION (R/W) (P) t VD;DAT t SU;STO MBD820 and ...
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... C-bus) a signal faster RESET SCL CLOCK CALENDAR PCF8593 OSCI SDA OSCO V SS SDA SCL 2 (I C-bus) Fig.23 Application diagram. 23 Product specification M 3: ETHOD DIRECT OUTPUT V DD RESET SDA MASTER TRANSMITTER/ RECEIVER SCL pull-up resistor BUS MBD825 PCF8593 ...
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... scale ( 0.53 1.07 0.36 9.8 0.38 0.89 0.23 9.2 0.021 0.042 0.014 0.39 0.015 0.035 0.009 0.36 REFERENCES JEDEC EIAJ MO-001AN ( 6.48 3.60 8.25 2.54 7.62 6.20 3.05 7.80 0.26 0.14 0.32 0.10 0.30 0.24 0.12 0.31 EUROPEAN PROJECTION Product specification PCF8593 SOT97-1 ( max. 10.0 0.254 1.15 8.3 0.39 0.01 0.045 0.33 ISSUE DATE 92-11-17 95-02-04 ...
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... REFERENCES JEDEC EIAJ MS-012AA detail 1.0 0.7 1.05 0.25 0.25 0.4 0.6 0.039 0.028 0.041 0.01 0.01 0.016 0.024 EUROPEAN PROJECTION Product specification PCF8593 SOT96 ( 0.7 0.1 0 0.028 0.004 0.012 ISSUE DATE 92-11-17 95-02-04 ...
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... Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds 300 C. When using a dedicated tool, all other leads can be soldered in one operation within seconds between 270 and 320 C. 26 Product specification PCF8593 ...
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... Philips. This specification can be ordered using the code 9398 393 40011. 1997 Mar 25 C COMPONENTS 2 C components conveys a license under the Philips’ system provided the system conforms to the I 27 Product specification PCF8593 2 C patent to use the 2 C specification defined by ...
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Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. + ...