MPC9658AC Freescale Semiconductor, MPC9658AC Datasheet

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MPC9658AC

Manufacturer Part Number
MPC9658AC
Description
IC PLL CLK GENERATOR 1:10 32LQFP
Manufacturer
Freescale Semiconductor
Type
Clock Generator, Fanout Distribution, Multiplexer , Zero Delay Bufferr
Datasheet

Specifications of MPC9658AC

Pll
Yes with Bypass
Input
LVCMOS, LVPECL
Output
LVCMOS
Number Of Circuits
1
Ratio - Input:output
1:10
Differential - Input:output
Yes/No
Frequency - Max
250MHz
Divider/multiplier
Yes/Yes
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
32-LQFP
Frequency-max
250MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC9658AC
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
MPC9658ACR2
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Freescale Semiconductor
Technical Data
© Freescale Semiconductor, Inc., 2004. All rights reserved.
3.3 V 1:10 LVCMOS PLL Clock
Generator
zero-delay buffer targeted for high performance low-skew clock distribution in
mid-range to high-performance telecom, networking and computing applications.
With output frequencies up to 250 MHz and output skews less than 120 ps the
device meets the needs of the most demanding clock applications. The
MPC9658 is specified for the temperature range of 0°C to +70°C.
Features
Functional Description
input reference clock. Normal operation of the MPC9658 requires the connection
of the QFB output to the feedback input to close the PLL feedback path (external
feedback). With the PLL locked, the output frequency is equal to the reference frequency of the device and VCO_SEL selects
the operating frequency range of 50 to 125 MHz or 100 to 250 MHz. The two available post-PLL dividers selected by VCO_SEL
(divide-by-2 or divide-by-4) and the reference clock frequency determine the VCO frequency. Both must be selected to match the
VCO frequency range. The internal VCO of the MPC9658 is running at either 2x or 4x of the reference clock frequency.
as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance.
lected input reference clock is bypassing the PLL and routed either to the output dividers or directly to the outputs. The PLL by-
pass configurations are fully static and the minimum clock frequency specification and all other PLL characteristics do not apply.
The outputs can be disabled (high-impedance) and the device reset by asserting the MR/OE pin. Asserting MR/OE also causes
the PLL to loose lock due to missing feedback signal presence at FB_IN. Deasserting MR/OE will enable the outputs and close
the phase locked loop, enabling the PLL to recover to normal operation.
LVCMOS except signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω trans-
mission lines. For series terminated transmission lines, each of the MPC9658 outputs can drive one or two traces giving the de-
vices an effective fanout of 1:16. The device is packaged in a 7x7 mm
The MPC9658 is a 3.3 V compatible, 1:10 PLL based clock generator and
The MPC9658 utilizes PLL technology to frequency lock its outputs onto an
The MPC9658 has a differential LVPECL reference input along with an external feedback input. The MPC9658 is ideal for use
The PLL_EN and BYPASS controls select the PLL bypass configuration for test and diagnosis. In this configuration, the se-
The MPC9658 is fully 3.3 V compatible and requires no external loop filter components. The inputs (except PCLK) accept
1:10 PLL based low-voltage clock generator
Supports zero-delay operation
3.3 V power supply
Generates clock signals up to 250 MHz
Maximum output skew of 120 ps
Differential LVPECL reference clock input
External PLL feedback
Drives up to 20 clock lines
32-lead LQFP packaging
32-lead Pb-free Package Available
Pin and function compatible to the MPC958
2
32-lead LQFP package.
PLL CLOCK GENERATOR
32-LEAD LQFP PACKAGE
32-LEAD LQFP PACKAGE
3.3 V LVCMOS 1:10
Pb-FREE PACKAGE
MPC9658
LOW VOLTAGE
CASE 873A-03
CASE 873A-03
FA SUFFIX
AC SUFFIX
Rev 5, 10/2004
MPC9658

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MPC9658AC Summary of contents

Page 1

... LVCMOS except signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω trans- mission lines. For series terminated transmission lines, each of the MPC9658 outputs can drive one or two traces giving the de- vices an effective fanout of 1:16. The device is packaged in a 7x7 mm © Freescale Semiconductor, Inc., 2004. All rights reserved. MPC9658 LOW VOLTAGE 3 ...

Page 2

... PLL_EN VCO_SEL BYPASS MR/ GND GND QFB V CC VCO_SEL MPC9658 2 ÷ Ref & VCO 1 ÷ 2 PLL 200 – 480 MHz FB Figure 1. MPC9658 Logic Diagram MPC9658 Figure 2. MPC9658 32-Lead Pinout (Top View ÷ QFB GND GND 8 Advanced Clock Drivers Device Data Freescale Semiconductor ...

Page 3

... Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Advanced Clock Drivers Device Data Freescale Semiconductor Type PECL reference clock signal PLL feedback signal input, connect to QFB ...

Page 4

... MIL-SPEC 883E Method 1012.1 Max Unit Condition V + 0.3 V LVCMOS CC 0.8 V LVCMOS mV LVPECL V –0.6 V LVPECL – Ω ±200 µ CC_PLL 20 mA All V CC Advanced Clock Drivers Device Data Freescale Semiconductor (2) or GND CC Pin Pins range CMR ...

Page 5

... Calculation of reference duty cycle limits Refer to APPLICATIONS INFORMATION 9. Output duty cycle (0.5 ± 400 ps ⋅ f 10. Refer to APPLICATIONS INFORMATION frequencies. 11. –3 dB point of PLL transfer characteristics. Advanced Clock Drivers Device Data Freescale Semiconductor (1) = 0°C to 70°C) A Min (2) ÷ 2 feedback 100 (3) ÷ 4 feedback ...

Page 6

... MHz REF = f 100 – 250 MHz f REF VCO = f 50 – 125 MHz f REF VCO and the filter capacitor C F Figure 3, the filter cut-off frequency is around Advanced Clock Drivers Device Data Freescale Semiconductor VCO n/a n/a n/a ⋅ REF ⋅ REF are F ...

Page 7

... With an output impedance of less than 20 Ω the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines, the reader is referred to Freescale Semiconductor Application Note AN1091. In most high performance clock networks, point-to-point distribution of signals is the method of choice point-to-point scheme, either series terminated or parallel terminated transmission lines can be used ...

Page 8

... Figure 9. PCLK MPC9658 AC Test Reference OutA OutB t = 3.8956 3.9386 Time (ns) Figure 8 should be used. In this case, the series MPC958 Output = 50 Ω Ω O Buffe S 14 Ω Ω Ω Ω Ω || 22Ω Ω Ω 25 Ω Ω Ω Ω Advanced Clock Drivers Device Data Freescale Semiconductor 14 ...

Page 9

... Figure 12. Output Duty Cycle (DC) T JIT(CC N+1 The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs Figure 14. Cycle-to-Cycle Jitter Advanced Clock Drivers Device Data Freescale Semiconductor V CC ÷ 2 PCLK V CC GND PCLK V CC ÷ 2 ...

Page 10

... A2 1.35 1.45 b 0.30 0.45 b1 0.30 0.40 c 0.09 0.20 c1 0.09 0.16 D 9.00 BSC D1 7.00 BSC e 0.80 BSC E 9.00 BSC E1 7.00 BSC L 0.50 0.70 L1 1.00 REF q 0˚ 7˚ REF R1 0.08 0.20 R2 0.08 --- S 0.20 REF Advanced Clock Drivers Device Data Freescale Semiconductor ...

Page 11

... Advanced Clock Drivers Device Data Freescale Semiconductor NOTES MPC9658 11 ...

Page 12

... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...

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