MPC9658AC Freescale Semiconductor, MPC9658AC Datasheet - Page 7

• Manufacturer Part Number: MPC9658AC
• Description: IC PLL CLK GENERATOR 1:10 32LQFP
• Manufacturer: Freescale Semiconductor
• Type: Clock Generator, Fanout Distribution, Multiplexer , Zero Delay Bufferr

Specifications of MPC9658AC

• Pll: Yes with Bypass
• Input: LVCMOS, LVPECL
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:10
• Differential - Input:output: Yes/No
• Frequency - Max: 250MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 250MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Advanced Clock Drivers Device Data
Freescale Semiconductor
Calculation of Part-to-Part Skew
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs of two or more
MPC9658 are connected together, the maximum overall
timing uncertainty from the common PCLK input to any output
is:
components: static phase offset, output skew, feedback
board trace delay, and I/O (phase) jitter:
is specified. I/O jitter numbers for other confidence factors
(CF) can be derived from
Table 8. Confidence Factor CF
The MPC9658 zero delay buffer supports applications
This maximum timing uncertainty consist of four
Due to the statistical nature of I/O jitter a RMS value (1σ)
± 1σ
± 2σ
± 3σ
± 4σ
± 5σ
± 6σ
CF
Any Q
Any Q
TCLK
Figure 4. MPC9658 Max. Device-to-Device Skew
QFB
QFB
t
Max. skew
SK(PP)
Common
Device 1
Device 1
Device 2
Device2
Probability of clock edge within the distribution
= t
(∅)
+ t
SK(O)
t
JIT(∅)
—t(ý)
Table
+t
+ t
SK(O)
PD, LINE(FB)
0.68268948
0.95449988
0.99730007
0.99993663
0.99999943
0.99999999
8.
+t
(∅)
t
SK(PP)
t
JIT(∅)
+ t
t
PD,LINE(FB)
+t
JIT(∅)
SK(O)
⋅ CF
layout and can be used to fine-tune the effective delay
through each device. In the following example calculation a
I/O jitter confidence factor of 99.7% (± 3σ) is assumed,
resulting in a worst case timing uncertainty from input to any
output of –214 ps to 224 ps relative to PCKL (f
FB = ³4, t
t
t
can be used for a more precise timing performance analysis.
Driving Transmission Lines
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user, the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20 Ω the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines, the reader is referred to Freescale Semiconductor
Application Note AN1091. In most high performance clock
networks, point-to-point distribution of signals is the method
of choice. In a point-to-point scheme, either series terminated
or parallel terminated transmission lines can be used. The
parallel technique terminates the signal at the end of the line
with a 50 Ω resistance to V
thus only a single terminated line can be driven by each
output of the MPC9658 clock driver. However, for the series
terminated case there is no DC current draw, thus the
outputs can drive multiple series terminated lines.
illustrates an output driving a single series terminated line
versus two series terminated lines in parallel. When taken to
its extreme, the fanout of the MPC9658 clock driver is
effectively doubled due to its capability to drive multiple lines.
SK(PP)
SK(PP)
The feedback trace delay is determined by the board
Due to the frequency dependence of the I/O jitter,
The MPC9658 clock driver was designed to drive high
This technique draws a fairly high level of DC current and
20
15
10
= [–70ps...80ps] + [–120ps...120ps] +
= [–214ps...224ps] + t
Figure 5. Max. I/O Jitter versus Frequency
5
0
200
jit(∅)
[(8ps ⋅ –3)...(8ps ⋅ 3)] + t
FB = ³ 2
= 8 ps RMS at f
250
Parameter: PLL Feedback Divider FB
I/O Phase Jitter versus Frequency
FB = ³ 4
300
FCO Frequency [MHz]
CC
VCO
÷ 2.
PD, LINE(FB)
350
= 400 MHz):
PD, LINE(FB)
400
REF
450
= 100 MHz,
Figure 6
MPC9658
Figure 5
500
7