MPC9658AC Freescale Semiconductor, MPC9658AC Datasheet - Page 5

• Manufacturer Part Number: MPC9658AC
• Description: IC PLL CLK GENERATOR 1:10 32LQFP
• Manufacturer: Freescale Semiconductor
• Type: Clock Generator, Fanout Distribution, Multiplexer , Zero Delay Bufferr

Specifications of MPC9658AC

• Pll: Yes with Bypass
• Input: LVCMOS, LVPECL
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:10
• Differential - Input:output: Yes/No
• Frequency - Max: 250MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 250MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Advanced Clock Drivers Device Data
Freescale Semiconductor
Table 6. AC Characteristics (V
10. Refer to
11. –3 dB point of PLL transfer characteristics.
1. AC characteristics apply for parallel output termination of 50 Ω to V
2. ÷ 2 PLL feedback (high frequency range) requires VCO_SEL = 0, PLL_EN = 1, BYPASS = 1 and MR/OE = 0.
3. ÷ 4 PLL feedback (low frequency range) requires VCO_SEL = 1, PLL_EN = 1, BYPASS = 1 and MR/OE = 0.
4. In bypass mode, the MPC9658 divides the input reference clock.
5. The input frequency f
6. V
7. Calculation of reference duty cycle limits: DC
8. Refer to
9. Output duty cycle is DC = (0.5 ± 400 ps ⋅ f
Symbol
t
V
t
t
t
t
JIT(PER)
PW,MIN
PLZ, HZ
PZL, LZ
JIT(CC)
t
t
t
f
f
CMR
JIT(∅)
and the input swing lies within the V
frequencies.
f
LOCK
V
sk(O)
t
BW
VCO
MAX
t
DC
REF
t
r
(∅)
PD
CMR
, t
PP
f
(6)
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
APPLICATIONS INFORMATION
APPLICATIONS INFORMATION
Input reference frequency
PLL mode, external feedback
Input reference frequency in PLL bypass mode
VCO lock frequency range
Output Frequency
Peak-to-peak input voltage (PCLK)
Common Mode Range (PCLK)
Input Reference Pulse Width
Propagation Delay (static phase offset)
Propagation Delay (PLL and divider bypass)
Output-to-output Skew
Output Duty Cycle
Output Rise/Fall Time
Output Disable Time
Output Enable Time
Cycle-to-cycle jitter
Period Jitter
I/O Phase Jitter f
PLL closed loop bandwidth
Maximum PLL Lock Time
REF
must match the VCO frequency range divided by the feedback divider ratio FB: f
VCO
f
(9)
VCO
= 500 MHz and ÷ 2 feedback, RMS (1σ)
CC
(8)
= 500 MHz and ÷ 4 feedback, RMS (1σ)
Characteristics
= 3.3 V ± 5%, T
PP
(5)
(11)
(7)
(AC) specification. Violation of V
OUT
for part-to-part skew calculation in PLL zero-delay mode.
for a jitter calculation for other confidence factors than 1 σ and a characteristic for other VCO
) Þ 100%. For example, the DC range at f
REF,MIN
A
= t
= 0°C to 70°C)
PW,MIN
(4)
f
PCLK to FB_IN
÷ 2 feedback
÷ 4 feedback
÷ 2 feedback
÷ 4 feedback
÷ 2 feedback
÷ 4 feedback
REF
any frequency
PCLK to Q0-9
= 100 MHz
⋅ f
REF
TT
⋅ 100% and DC
.
(10)
(2)
(3)
(3)
(4)
(3)
(5)
CMR
(1)
(T ÷ 2)–400
or V
–125
Min
100
200
100
500
–70
1.2
2.0
1.0
0.1
50
50
PP
0
impacts static phase offset t
REF,MAX
OUT
= 100MHz is 46% < DC < 54%. T = output period.
6 – 20
T ÷ 2
2 – 8
Typ
= 100% – DC
(T ÷ 2)+400
V
CC
1000
+125
Max
250
125
250
500
250
125
+80
120
4.0
1.0
7.0
6.0
5.5
6.5
REF
80
80
10
REF,MIN
–0.9
= f
(∅)
VCO
.
.
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
mV
ms
ns
ps
ps
ns
ps
ps
ns
ns
ns
ps
ps
ps
ps
÷ FB.
V
PLL locked
PLL locked
PLL locked
PLL locked
LVPECL
LVPECL
PLL locked
0.55 to 2.4 V
Condition
CMR
MPC9658
range
5