LMX2433TMX/NOPB National Semiconductor, LMX2433TMX/NOPB Datasheet - Page 36

• Manufacturer Part Number: LMX2433TMX/NOPB
• Description: IC SYNTHESIZER DL 3.6GHZ 20TSSOP
• Manufacturer: National Semiconductor
• Series: PLLatinum™r
• Type: PLL Frequency Synthesizerr

Specifications of LMX2433TMX/NOPB

• Pll: Yes with Bypass
• Input: CMOS
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 3:2
• Differential - Input:output: Yes/No
• Frequency - Max: 3.6GHz, 1.7GHz
• Divider/multiplier: No/No
• Voltage - Supply: 2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 3.6GHz
• For Use With: LMX2433EVAL - EVALUATION BOARD FOR LMX2433
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMX2433TMX

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1.0 Functional Description
1.8.3 Digital Filtered Lock Detect Output
A digital filtered lock detect status generated from the phase
detector is also available on the Ftest/LD output pin if se-
lected. The lock detect digital filter compares the difference
bewteen the phases of the inputs to the PFD to an RC
generated delay of approximately 15 ns. If the phase error is
less than the 15 ns RC delay for 5 consecutive reference
Similarly, three separate digital filtered lock detect signals
are routed to the multiplexer. Two of these monitor the lock
status of the individual synthesizers. The third detects the
condition when both the RF and IF synthesizers are in a
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cycles, the PLL enters a locked state (HIGH). Once in lock,
the RC delay is changed to approximately 30 ns. Once the
phase error becomes greater than the 30 ns RC delay, the
PLL falls out of lock (LOW). When the PLL is in powerdown
mode, the Ftest/LD output is forced LOW. A flow chart of the
digital filtered lock detect output is shown below.
locked state. External circuitry is not required when the
digital filtered lock detect option is selected. Refer to Section
2.10 for details on how to program the different digital filtered
lock detect options.
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