LFX125EB-04F256I LATTICE SEMICONDUCTOR, LFX125EB-04F256I Datasheet - Page 31

• Manufacturer Part Number: LFX125EB-04F256I
• Description: FPGA ispXPGA® Family 139K Gates 1936 Cells EECMOS Technology 2.5V/3.3V 256-Pin FBGA
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LFX125EB-04F256I

• Package: 256FBGA
• Family Name: ispXPGA®
• Device Logic Units: 1936
• Device System Gates: 139000
• Number Of Registers: 3800
• Typical Operating Supply Voltage: 2.5|3.3 V
• Maximum Number Of User I/os: 160
• Ram Bits: 94208
• Re-programmability Support: Yes

Lattice Semiconductor
Figure 23. LVPECL Driver with Three Resistor Pack
ispXPGA 125B/C & ispXPGA 125EB/EC External Switching Characteristics
t
t
t
t
t
t
t
t
t
t
1. Only available for ispXPGA 125B and ispXPGA 125EB (2.5V/3.3V) devices.
Parameter
CO
S
H
SINDLY
HINDLY
COPLL
SPLL
HPLL
SINDLYPLL
HINDLYPLL
Global Clock Input to
Output
Global Clock Input Setup
Global Clock Input Hold
Global Clock Input Setup
Global Clock Input Hold
Global Clock Input to
Output
Global Clock Input Setup
Global Clock Input Hold
Global Clock Input Setup
Global Clock Input Hold
ispXPLD Emulated
LVPECL Buffer
Description
Over Recommended Operating Conditions
PIO Output Register
PIO Input Register without input
delay
PIO Input Register without input
delay
PIO Input Register with input delay
PIO Input Register with input delay
PIO Output Register using PLL
without delay
PIO Input Register without input
delay using PLL without delay
PIO Input Register without input
delay using PLL without delay
PIO Input Register with input delay
using PLL without delay
PIO Input Register with input delay
using PLL without delay
1/4 of Bourns P/N
CAT 16-PC4F12
Rs
Rs
Conditions
A
27
Zo
Zo
Min.
-1.9
-3.0
2.7
3.1
0.0
0.9
5.1
—
—
0
-5
1
Max.
5.3
3.6
—
—
—
—
—
—
—
—
ispXPGA Family Data Sheet
Min.
-1.8
-2.8
3.3
0.0
2.9
0.1
1.0
5.5
—
—
-4
Max.
to LVPECL
5.7
3.9
differential
—
—
—
—
—
—
—
—
receiver
Min.
-1.5
-2.4
3.3
3.8
0.0
0.3
1.2
6.3
—
—
-3
Max.
6.6
4.5
—
—
—
—
—
—
—
—
Timing v.0.3
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns