LFX125EB-04F256I LATTICE SEMICONDUCTOR, LFX125EB-04F256I Datasheet - Page 17

• Manufacturer Part Number: LFX125EB-04F256I
• Description: FPGA ispXPGA® Family 139K Gates 1936 Cells EECMOS Technology 2.5V/3.3V 256-Pin FBGA
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LFX125EB-04F256I

• Package: 256FBGA
• Family Name: ispXPGA®
• Device Logic Units: 1936
• Device System Gates: 139000
• Number Of Registers: 3800
• Typical Operating Supply Voltage: 2.5|3.3 V
• Maximum Number Of User I/os: 160
• Ram Bits: 94208
• Re-programmability Support: Yes

Lattice Semiconductor
Figure 13. EBR Synchronous Read Timing Diagram
Synchronous Write: The WE signal controls the synchronous write operation. When the WE signal is high, the
write operation begins. Once the address and data are present and the Output Enable (OE) is active, a rising clock
edge (or falling edge depending on polarity) causes the data to be stored into the EBR. Figure 14 illustrates the
synchronous write timing.
Figure 14. EBR Synchronous Write Timing Diagram
Asynchronous Read: The WE signal controls the asynchronous read operation. When the WE signal is low, the
read operation begins. Shortly after the address is present, the stored data is available on the DATA port. Figure 15
illustrates the asynchronous read timing. For more information about the EBR, refer to TN1028
Usage
Figure 15. EBR Asynchronous Read Timing Diagram
Guidelines.
ADDR
ADDR
ADDR
DATA
DATA
DATA
CLK
CLK
WE
WE
WE
CE
OE
OE
ADDR0
t
EBWEDIS
t
EBWEDIS
t
t
EBCES
EBWES
t
EBWES
t
EBADDS
t
EBARAD_H
DATA0
t
EBARADO
Invalid Data
Invalid Data
t
t
EBDATAH
EBCPW
t
t
EBCO
EBPW
WRITE
t
EBDATAS
13
Valid Data
DATA1
t
t
EBADDH
EBADDH
ADDR1
t
t
EBOEDIS
EBOEDIS
WRITE
t
EBADDS
t
ispXPGA Family Data Sheet
t
EBOEEN
EBOEEN
t
EBWEH
t
t
EBWEH
EBCEH
Valid Data
DATA1
t
t
EBWEEN
EBWEEN
ADDR2
ispXPGA Memory