IPPOSPHYP3 Altera, IPPOSPHYP3 Datasheet - Page 53

• Manufacturer Part Number: IPPOSPHYP3
• Manufacturer: Altera

Specifications of IPPOSPHYP3

• Lead Free Status / RoHS Status: Not Compliant

Chapter 3: Functional Description
Interface Signals
Table 3–12. POS-PHY Level 2 Receive Interface (Part 2 of 3)
© November 2009 Altera Corporation
rmod
rsop
reop
rerr
renb
radr[4:0]
Signal
(2)
PHY to link
PHY to link
PHY to link
PHY to link
Link to PHY Receive multi-PHY read enable signal. renb is used to initiate reads from the receive
Link to PHY Receive read address signals. The radr signal is used to select the FIFO buffer (and
Direction
The receive word modulo signal. rmod indicates the size of the current word. rmod is
only used during the last word transfer of a packet, when reop is asserted. During a
packet transfer every word must be complete except the last word, which can be
composed of 1 or 2 bytes. rmod set high indicates a 1-byte word (present on MSBs,
LSBs are discarded); rmod set low indicates a 2-byte word. The PHY-layer device tri-
states rmod when renb is high. rmod is also tri-stated when either the null-PHY
address (1Fh), or an address not matching the PHY-layer device address, is presented
on the radr signals when renb is sampled high (has been deasserted during the
previous clock cycle).
Receive start of packet signal. rsop marks the first word of a packet transfer. The
PHY-layer device must assert rsop for every packet. The PHY-layer device tri-states
rsop when renb is high. rsop is also tri-stated when either the null-PHY address
(1Fh), or an address not matching the PHY-layer device address, is presented on the
radr signals when renb is sampled high (has been deasserted during the previous
clock cycle).
The receive end of packet signal. reop marks the end of packet on the rdat bus.
During this same cycle rmod is used to indicate if the last word has 1 or 2 bytes. rsop
must not be high when reop is high. This provides support for one or two bytes
packets, as indicated by the value of rmod. The PHY-layer device tri-states reop when
renb is high. reop is also tri-stated when either the null-PHY address (0x1F), or an
address not matching the PHY-layer device address, is presented on the radr signals
when renb is sampled high (has been deasserted during the previous clock cycle).
The receive error indicator signal. rerr is used to indicate that the current packet is
aborted and should be discarded. rerr can only be asserted during the last word
transfer of a packet. Conditions that can cause rerr to be set may be, but are not
limited to, FIFO buffer overflow, abort-sequence detection, missing SOP, missing EOP,
and parity errors. The PHY-layer device tri-states rerr when renb is high. terr is
asserted at its input. rerr is valid only when rval is asserted. rerr is also tri-stated
when either the null-PHY address (1Fh), or an address not matching the PHY-layer
device address, is presented on the radr signals when renb is sampled high (has
been deasserted during the previous clock cycle).
FIFO buffers. The POS-PHY specification supports both byte-level and packet-renb
transfer. Packet-level transfer operates with a selection phase when renb is
deasserted and a transfer phase when renb is asserted. While renb is asserted,
radr is used for polling prpa. Byte-level transfer works on a cycle basis. When renb
is asserted, data is transferred from the selected PHY and radr is used to select the
PHY. Nothing happens when renb is deasserted high. In byte-level transfer mode
polling is not possible; packet availability is directly indicated by drpa[x]. renb
must operate in conjunction with rfclk to access the FIFO buffers at a high enough
rate to prevent FIFO buffer overflows. The system may deassert renb at anytime it is
unable to accept another byte.
hence port) that is read from using the renb signal. For packet-level transfer, radr is
also used to determine the FIFO buffers whose packet available signal is polled on the
prpa output. Address 1Fh is the null-PHY address and must not be responded to by
any PHY-layer device.
Preliminary
Description
POS-PHY Level 2 and 3 Compiler User Guide
3–25