IPPOSPHYP3 Altera, IPPOSPHYP3 Datasheet - Page 26

• Manufacturer Part Number: IPPOSPHYP3
• Manufacturer: Altera

Specifications of IPPOSPHYP3

• Lead Free Status / RoHS Status: Not Compliant

2–14
POS-PHY Level 2 and 3 Compiler User Guide
3. Add the following files to the project from the \posphy_l2_l3\lib directory:
4. Check that the absolute path to your third-party simulation tool is set. Set the path
5. On the Processing menu, point to Start and click Start Analysis & Elaboration.
6. On the Assignments menu, click Settings. The Settings window appears. Expand
7. In Tool name, select a simulator tool from the list.
8. In the Test Benches window, click New. The New Test Bench Settings window
9. In the New Test Bench Settings window, enter the information described in
Table 2–2. NativeLink Test Bench Settings
Test bench name
Top-level module in test bench
Design instance name in test bench
Run for
Test bench files
Notes to table:
(1) Use mtx for Tx simulations.
(2) If you are preparing a VHDL simulation, use auk_pac_mrx_ref_tb.vhd in the vhdl directory.
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The files must be in the order shown, from top to bottom, which is the order of
compilation. Use the Up and Down buttons in the New Project Wizard: Add Files
window to order the files.
from EDA Tool Options in the Options dialog box (Tools menu).
1
EDA Tool Settings and select Simulation.
In EDA Netlist Writer options, select Verilog from the list for Format for output
netlist (Select VHDL if you are preparing a VHDL simulation).
In NativeLink settings, select the Compile test bench option and then click Test
Benches . The Test Benches window appears.
appears.
Table 2–2
table, browse to the files in your project.
Figure 2–16
auk_pac_gen_if.vhd
auk_pac_functions.vhd
auk_pac_components.vhd
If the analysis and elaboration is not successful, fix the error before moving
to the next step.
(see also
shows the testbench settings for a receive simulation.
Parameter
Figure 2–16 on page
Preliminary
2–15). To enter the files described in the
<any name>
auk_pac_mrx_ref
mrx
100 ns
auk_pac_mrx_ref_tb.v
(1)
© November 2009 Altera Corporation
Setting/File Name
(1)
Chapter 2: Getting Started
(2)
Simulate the Design