PNX1311EH/G NXP Semiconductors, PNX1311EH/G Datasheet - Page 359

• Manufacturer Part Number: PNX1311EH/G
• Manufacturer: NXP Semiconductors

Specifications of PNX1311EH/G

• Lead Free Status / RoHS Status: Compliant

PNX1300/01/02/11 Data Book
fsqrtflags
SYNTAX
FUNCTION
DESCRIPTION
rsrc1 and stores a bit vector representing the exception flags into rdest. The argument value is in IEEE single-
precision floating-point format; the result is an integer bit vector. The bit vector stored in rdest has the same format as
the IEEE exception bits in the PCSW. The exception flags in PCSW are left unchanged by this operation. Rounding is
according to the IEEE rounding mode bits in PCSW. If the argument is denormalized, zero is substituted before
computing the squareroot, and the IFZ bit in the result is set. If the result is denormalized, and the OFZ flag in the
PCSW is set.
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
A-61
r60 = 0xc0400000 (–3.0)
r40 = 0x40400000 (3.0)
r10 = 0, r40 = 0x40400000 (3.0)
r20 = 1, r40 = 0x40400000 (3.0)
r82 = 0x00c00000 (1.763241526e–38)
r84 = 0x7f800000 (+INF)
r70 = 0x7f7fffff (3.402823466e+38)
r80 = 0x00400000 (5.877471754e-39)
The
The
[ IF rguard ] fsqrtflags rsrc1 → rdest
if rguard then
fsqrtflags
fsqrtflags
rdest ← ieee_flags(square_root((float)rsrc1))
31
0
Initial Values
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
operation computes the IEEE exceptions that would result from computing the squareroot of
PRELIMINARY SPECIFICATION
IEEE status flags from floating-point square root
fsqrtflags r60 → r90
fsqrtflags r40 → r95
IF r10 fsqrtflags r40 → r100
IF r20 fsqrtflags r40 → r110
fsqrtflags r82 → r112
fsqrtflags r84 → r113
fsqrtflags r70 → r120
fsqrtflags r80 → r125
Operation
7
0
OFZ
6
IFZ
5
INV
4
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Recovery
Issue slots
r90 ← 0x10 (INV)
r95 ← 0x2 (INX)
no change, since guard is false
r110 ← 0x2 (INX)
r112 ← 0x2 (INX)
r113 ← 0
r120 ← 0x2 (INX)
r125 ← 0x20 (IFZ)
OVF
3
Philips Semiconductors
fsqrt readpcsw
UNF
ATTRIBUTES
2
SEE ALSO
Result
INX
1
DBZ
0
ftough
111
No
17
16
—
1
2