SAA7113H/V2,518 Trident Microsystems, Inc., SAA7113H/V2,518 Datasheet - Page 62

• Manufacturer Part Number: SAA7113H/V2,518
• Manufacturer: Trident Microsystems, Inc.

Specifications of SAA7113H/V2,518

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Philips Semiconductors
9397 750 14232
Product data sheet
Fig 38. Vertical timing diagram for 50 Hz [nominal input signal, VNL in normal mode (VNOI = 00), HPLL in VCR or
(1) VREF range short or long can be programmed via I
(2) FID changing line number and polarity programmable via VSTA8 to VSTA0 and FIDP (see
(3) The inactive going edge of the V123-signal indicates whether the field is odd or even. If HREF is active during the falling
input CVBS
RTS0/1 HREF
RTS0/1 VREF
RTS0/1 VREF
RTS0/1 VS
RTS0/1 ODD
RTS0/1 V123
RTS0/1 FID
input CVBS
RTS0/1 HREF
RTS0/1 VREF
RTS0/1 VREF
RTS0/1 VS
RTS0/1 ODD
RTS0/1 V123
RTS0/1 FID
HREF: selectable on RTS0 and/or RTS1 via I
ODD: selectable on RTS0 and/or RTS1 via I
VS: selectable on RTS0 and/or RTS1 via I
V123: selectable on RTS0 and/or RTS1 via I
VREF: selectable on RTS0 and/or RTS1 via I
FID: selectable on RTS0 and/or RTS1 via I
bypassed during VREF = 0 if I
NTSC, phase error correcting for PAL) is disabled during VREF = 0.
edge of V123, the field is odd. If HREF is inactive during the falling edge of V123, the field is even. The specific position of
the slope is dependent on the internal processing delay and may change a few clock cycles from version to version.
fast mode (HTC = 01 or 11)]
(2)
(2)
VRLN = 1
VRLN = 0
VRLN = 1
VRLN = 0
(3)
(3)
622
310
(1)
(1)
(1)
(1)
623
311
2
C-bus bit VBLB is set to logic 1. The chrominance delay line (chrominance-comb filter for
624
312
625
313
2
2
C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = Bh.
C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = Fh.
2
2
C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = Ah.
2
2
C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = Ch.
C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = Eh.
C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = 7h.
1
314
Rev. 02 — 9 May 2005
2
C-bus bit VRLN. The luminance peaking and the chrominance trap are
2
315
(a) 1st field
(b) 2nd field
3
316
4
317
5
318
6
319
7
320
Table
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
9-bit video input processor
67
53).
8
335
2/LLC
499
SAA7113H
22
336
2/LLC
23
337
mhb336
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