SAA7113H/V2,518 Trident Microsystems, Inc., SAA7113H/V2,518 Datasheet - Page 42

• Manufacturer Part Number: SAA7113H/V2,518
• Manufacturer: Trident Microsystems, Inc.

Specifications of SAA7113H/V2,518

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Philips Semiconductors
9397 750 14232
Product data sheet
9.2.11 Subaddress 0Ah
Table 37:
[1]
Table 38:
Function
Aperture factor = 0.5
Aperture factor = 1.0
Update time interval for analog AGC value (UPTCV)
Horizontal update (once per line)
Vertical update (once per field)
Vertical blanking luminance bypass (VBLB)
Active luminance processing
Chrominance trap and peaking stage are disabled
during VBI lines determined by VREF = 0 (see
Aperture band-pass (center frequency) (BPSS)
Center frequency = 4.1 MHz
Center frequency = 3.8 MHz
Center frequency = 2.6 MHz
Center frequency = 2.9 MHz
Prefilter active (PREF); see
Bypassed
Active
Chrominance trap bypass (BYPS)
Chrominance trap active; default for CVBS mode
Chrominance trap bypassed; default for S-video mode
Offset
255 (bright)
128 (ITU level)
0 (dark)
Not to be used with bypassed chrominance trap.
Luminance control subaddress 09h (D7 to D0)
Luminance brightness control subaddress 0Ah (D7 to D0)
Control bits D7 to D0
BRIG7 BRIG6 BRIG5 BRIG4 BRIG3 BRIG2 BRIG1 BRIG0
1
1
0
Rev. 02 — 9 May 2005
[1]
[1]
[1]
Figure
1
0
0
11,
Figure
1
0
0
Table
12,
Figure
46)
1
0
0
Control bit
APER1
APER0
APER1
APER0
UPTCV
UPTCV
VBLB
VBLB
BPSS1
BPSS0
BPSS1
BPSS0
BPSS1
BPSS0
BPSS1
BPSS0
PREF
PREF
BYPS
BYPS
14,
…continued
1
0
0
Figure 16
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
9-bit video input processor
1
0
0
Logic level Data bit
1
0
1
1
0
1
0
1
0
0
0
1
1
0
1
1
0
1
0
1
SAA7113H
and
Figure 17
1
0
0
D1
D0
D1
D0
D2
D2
D3
D3
D5
D4
D5
D4
D5
D4
D5
D4
D6
D6
D7
D7
1
0
0
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