SAA7113H/V2,518 Trident Microsystems, Inc., SAA7113H/V2,518 Datasheet - Page 48

• Manufacturer Part Number: SAA7113H/V2,518
• Manufacturer: Trident Microsystems, Inc.

Specifications of SAA7113H/V2,518

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Philips Semiconductors
9397 750 14232
Product data sheet
Table 51:
RTS1 output control
3-state, pin RTS1 is used as DOT input (see
VIPB (subaddress 11h, bit 1) = 0: reserved
VIPB (subaddress 11h, bit 1) = 1: LSBs of the 9-bit ADCs
GPSW1
Horizontal Lock (HL) indicator; selectable via HLSEL
(subaddress 11h, bit 4)
VL (vertical and horizontal lock)
DL (vertical and horizontal lock and color detected)
PLIN (PAL/SECAM sequence; LOW: PAL/DR line is
present)
HREF_HS, horizontal reference signal: indicates valid
data on the VPO-bus. The positive slope marks the
beginning of a new active line. The pulse width is
dependent on the data type selected by the control
registers LCR2 to LCR24 (subaddress 41h to 57h;
see
HS, programmable width in LLC8 steps via HSB7 to
HSB0 and HSS7 to HSS0 (subaddress 06h and 07h), fine
position adjustment in LLC2 steps via HDEL1 to HDEL0
(subaddress 10h, bits 5 and 4)
HQ (HREF gated with VREF)
ODD, field identifier; HIGH = odd field; see vertical timing
diagrams
VS (vertical sync); see vertical timing diagrams
and
V123 (vertical pulse); see vertical timing diagrams
Figure 38
VGATE (programmable via VSTA8 to VSTA0 and VSTO8
to VSTO0, subaddresses 15h, 16h and 17h)
VREF (programmable in two positions via VRLN,
subaddress 10h, bit 3)
FID (position and polarity programmable via VSTA 8 to
VSTA0, subaddresses 15h and 17h and FIDP,
subaddress 13h, bit 3)
•
•
•
•
Table 7
Figure 39
HLSEL = 0: standard horizontal lock indicator
HLSEL = 1: fast horizontal lock indicator (use is not
recommended for sources with unstable timebase
e.g. VCRs)
data type 0 to 6, 8 to 15: HIGH period
1440 LLC-cycles (720 samples; see
data type 7 (upsampled raw data): HIGH period
programmable in LLC8 steps via HSB7 to HSB0,
HSS7 to HSS0 (subaddress 06h and 07h), fine
position adjustment via HDEL1 to HDEL0
(subaddress 10h, bits 5 and 4)
Figure 38
and
RTS1 output control subaddress 12h
and
Figure 39
Table
and
62)
Figure 39
Rev. 02 — 9 May 2005
Figure
Table
Figure 38
37)
22)
Control bits D7 to D4
RTSE13 RTSE12 RTSE11 RTSE10
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
9-bit video input processor
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SAA7113H
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
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