PNX1301EH/G,557 Trident Microsystems, Inc., PNX1301EH/G,557 Datasheet - Page 382

• Manufacturer Part Number: PNX1301EH/G,557
• Manufacturer: Trident Microsystems, Inc.

Specifications of PNX1301EH/G,557

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Philips Semiconductors
Sum of products of signed 16-bit halfwords
SYNTAX
FUNCTION
DESCRIPTION
halfwords of rsrc1 and rsrc2; the two products are summed, and the result is written to rdest. All values are considered
signed; thus, the intermediate products and the final sum of products are signed. All intermediate computations are
performed without loss of precision; the final sum of products is clipped into the range [0x80000000..0x7fffffff] before
being written into rdest.
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
r30 = 0x00020003, r40 = 0x00010002
r10 = 0, r60 = 0xff9c0064, r70 = 0x0064ff9c
r20 = 1, r60 = 0xff9c0064, r70 = 0x0064ff9c
r30 = 0x00020003, r70 = 0x0064ff9c
As shown below, the
The
[ IF rguard ] ifir16 rsrc1 rsrc2 → rdest
if rguard then
rsrc1
rdest ← sign_ext16to32(rsrc1<31:16>) × sign_ext16to32(rsrc2<31:16>) +
ifir16
31
sign_ext16to32(rsrc1<15:0>) × sign_ext16to32(rsrc2<15:0>)
signed
Initial Values
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
ifir16
Full-precision
33-bit result
15
rdest
operation computes two separate products of the two pairs of corresponding 16-bit
32
31
signed
ifir16 r30 r40 → r50
IF r10 ifir16 r60 r70 → r80
IF r20 ifir16 r60 r70 → r90
ifir16 r30 r70 → r100
0
Clip to [2
signed
signed
31
–1..–2
Operation
PRELIMINARY SPECIFICATION
rsrc2
31
31
]
PNX1300/01/02/11 DSPCPU Operations
signed
×
0
0
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
ifir8ii ifir8ui ufir8uu
r50 ← 0x8
no change, since guard is false
r90 ← 0xffffb1e0
r100 ← 0xffffff9c
+
15
ATTRIBUTES
SEE ALSO
ifir16
signed
Result
×
ifir16
dspmul
2, 3
No
93
—
0
2
3
A-84