PNX1301EH/G,557 Trident Microsystems, Inc., PNX1301EH/G,557 Datasheet - Page 207

• Manufacturer Part Number: PNX1301EH/G,557
• Manufacturer: Trident Microsystems, Inc.

Specifications of PNX1301EH/G,557

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Philips Semiconductors
13.4
Table 13-5
for an autonomous boot procedure. For the host-assisted
Table 13-5. Serial boot EEPROM contents
Line
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
11
0
1
2
3
4
5
6
7
8
9
1: autonomous
1: 256 or more
DETAILED EEPROM CONTENTS
0: host assist.
0: 128 lines
sdram PLL
boot type
bypass
#lines
bit 7
shows the serial EEPROM contents needed
lines
—
sdram PLL dis-
nal PCI_CLK
enable inter-
DRAM_CACHEABLE_LIMIT address [31:24] (must be byte 3 of MMIO_BASE + 0x100008)
DRAM_CACHEABLE_LIMIT address [23:16] (must be byte 2 of MMIO_BASE + 0x100008)
DRAM_CACHEABLE_LIMIT address [15:8] (must be byte 1 of MMIO_BASE + 0x100008)
DRAM_CACHEABLE_LIMIT address [7:0] (must be byte 0 of MMIO_BASE + 0x100008)
bit 6
able
—
DRAM_BASE address [31:24] (must be byte 3 of MMIO_BASE + 0x100000)
DRAM_BASE address [23:16] (must be byte 2 of MMIO_BASE + 0x100000)
DRAM_LIMIT address [31:24] (must be byte 3 of MMIO_BASE + 0x100004)
DRAM_LIMIT address [23:16] (must be byte 2 of MMIO_BASE + 0x100004)
DRAM_BASE address [15:8] (must be byte 1 of MMIO_BASE + 0x100000)
DRAM_LIMIT address [15:8] (must be byte 1 of MMIO_BASE + 0x100004)
DRAM_BASE address [7:0] (must be byte 0 of MMIO_BASE + 0x100000)
DRAM_LIMIT address [7:0] (must be byte 0 of MMIO_BASE + 0x100004)
SDRAM size[2:0]
cpu PLL bypass
prefetchable
0:no 1:yes
101: 16MB
110: 32MB
111: 64MB
000: 1MB
001: 1MB
010: 2MB
011: 4MB
100: 8MB
SDRAM
bit 5
—
MMIO_BASE address [31:24] (must be 0xEF)
MMIO_BASE address [23:16] (must be 0xF0)
MMIO_BASE address [15:8] (must be 0x04)
MMIO_BASE address [15:8] (must be 0x00)
Subsystem Vendor ID, 8 msb
cpu PLL disable
Subsystem Vendor ID, 8 lsb
DRAM_BASE value [31:24]
DRAM_BASE value [23:16]
DRAM_LIMIT value [31:24]
DRAM_LIMIT value [23:16]
MMIO_BASE value [31:24]
MMIO_BASE value [23:16]
DRAM_BASE value [15:8]
DRAM_LIMIT value [15:8]
MMIO_BASE value [15:8]
DRAM_BASE value [7:0]
DRAM_LIMIT value [7:0]
MMIO_BASE value [7:0]
Subsystem ID, 8 msb
Subsystem ID, 8 lsb
MM_CONFIG[15:8]
bit 4
MM_CONFIG[7:0]
PLL_RATIOS[7:0]
—
—
byte count [7:0]
Data Byte
boot procedure, only the contents up to line nine are
needed.
Note that the 32-bit words in the serial EEPROM are not
stored on 32-bit word-aligned addresses.
PRELIMINARY SPECIFICATION
sdram ratio
bit 3
—
BOOT_CLK[1:0]
00: 100 MHz
01: 75 MHz
10: 50 MHz
11: 33 MHz
MM_CONFIG[19:16]
bit 2
byte count [10:8]
cpu ratio[2:0]
EEPROM
0: 100 KHz
1: 400 KHz
clock
bit 1
System Boot
1: rapid ATE
Test Mode
0: normal
bit 0
13-7