CP3UB26Y98NEPX National Semiconductor, CP3UB26Y98NEPX Datasheet - Page 83

• Manufacturer Part Number: CP3UB26Y98NEPX
• Manufacturer: National Semiconductor

Specifications of CP3UB26Y98NEPX

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Not Compliant

16.2
Table 31 lists the RNG registers.
16.2.1
The RNGCST register provides control and status bits for
the RNG module. This register is cleared at reset.
RNGE
DVALID
IMASK
15
RNGDIVH
Reserved
RNGDIVL
RNGCST
RNGD
Name
RNG Control and Status Register (RNGCST)
RANDOM NUMBER GENERATOR
REGISTER SET
6
The Random Number Generator Enable bit
enables the operation of the RNG. When this
bit is clear, the RNG module is disabled, and
both RNG oscillators are suspended.
0 – RNG module disabled.
1 – RNG module enabled.
The Data Valid bit indicates whether valid
(random) data is available in the RNGD regis-
ter. This bit is cleared when the RNGD regis-
ter is read.
0 – RNGD register holds invalid data.
1 – RNGD register holds valid data.
The Interrupt Mask bit controls whether an in-
terrupt request (IRQ3) will be asserted when
valid (random) data is available in the RNGD
register.
0 – RNG interrupt disabled.
1 – RNG interrupt enabled.
Table 34 RNG Registers
IMSK
5
FF F280h
FF F282h
FF F284h
FF F286h
Address
4
Reserved
RNG Divisor Register
RNG Divisor Register
RNG Data Register
RNG Control and
2
Status Register
Description
DVALID RNGE
High
Low
1
0
83
16.2.2
The RNGD register holds random data generated by the
RNG module. After reading the register, it is cleared and the
DVALID bit of the RNGCST register is cleared. When a new
word of valid (random) data becomes available in the RNGD
register, the DVALID bit is set and (if enabled) and interrupt
request is asserted.
16.2.3
This register holds the two most significant bits of the
RNGDIV clock divisor. See the description of the RNGDIVL
register.
16.2.4
This register holds the 16 least significant bits the RNGDIV
clock divisor.
The RNGDIV clock divisor is used to generate the sampling
strobe for loading random bits into the shift register. The di-
visor is applied to the System Clock source. The maximum
frequency after division is 800 Hz. For example, a System
Clock frequency of 24 MHz would require an RNGDIV value
of 30,000 (7530h) or greater. The default RNGDIV value is
0000 83D6h.
15
15
15
RNG Data Register (RNGD)
RNG Divisor Register High (RNGDIVH)
RNG Divisor Register Low (RNGDIVL)
Reserved
RNGDIV15:0
RNGD15:0
2
RNGDIV17:16
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