CP3UB26Y98NEPX National Semiconductor, CP3UB26Y98NEPX Datasheet - Page 44

• Manufacturer Part Number: CP3UB26Y98NEPX
• Manufacturer: National Semiconductor

Specifications of CP3UB26Y98NEPX

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Not Compliant

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9.6.1
The Device A Address Counter register is a 32-bit, read/
write register. It holds the current 24-bit address of either the
source data item or the destination location, depending on
the state of the DIR bit in the CNTLn register. The ADA bit
of DMACNTLn register controls whether to adjust the point-
er in the ADCAn register by the step size specified in the
INCA field of DMACNTLn register. The upper 8 bits of the
ADCAn register are reserved and always clear.
31
Reserved
DMACNTL2
DMACNTL3
DMASTAT2
DMASTAT3
ADCA2
ADRA2
ADCB2
ADRB2
ADCA3
ADRA3
ADCB3
ADRB3
BLTC2
BLTR2
BLTC3
BLTR3
Name
Device A Address Counter Register (ADCAn)
24
Table 18 DMA Controller Registers
23
FF F84Ch
FF F85Ch
FF F86Ch
FF F87Ch
FF F85Eh
FF F87Eh
FF F840h
FF F844h
FF F848h
FF F850h
FF F854h
FF F860h
FF F864h
FF F868h
FF F870h
FF F874h
Address
Device A Address Counter
Block Length Register
Block Length Register
DMA Control Register
DMA Control Register
DMA Status Register
DMA Status Register
Device A Address
Device A Address
Device B Address
Device B Address
Device A Address
Device A Address
Device B Address
Device B Address
Counter Register
Counter Register
Counter Register
Counter Register
Counter Register
Counter Register
Block Length
Block Length
Description
Register
Register
Register
Register
0
44
9.6.2
The Device A Address register is a 32-bit, read/write regis-
ter. It holds the 24-bit starting address of either the next
source data block, or the next destination data area, according
to the DIR bit in the DMACNTLn register. The upper 8 bits of
the ADRAn register are reserved and always clear.
9.6.3
The Device B Address Counter register is a 32-bit, read/
write register. It holds the current 24-bit address of either the
source data item, or the destination location, according to
the DIR bit in the CNTLn register. The ADCBn register is up-
dated after each transfer cycle by INCB field of the
DMACNTLn register according to ADB bit of the
DMACNTLn register. In direct (flyby) mode, this register is
not used. The upper 8 bits of the ADCBn register are re-
served and always clear.
9.6.4
The Device B Address register is a 32-bit, read/write regis-
ter. It holds the 24-bit starting address of either the next
source data block or the next destination data area, accord-
ing to the DIR bit in the CNTLn register. In direct (flyby )
mode, this register is not used. The upper 8 bits of the AD-
CRBn register are reserved and always clear.
9.6.5
The Block Length Counter register is a 16-bit, read/write
register. It holds the current number of DMA transfers to be
executed in the current block. BLTCn is decremented by one
after each transfer cycle. A DMA transfer may consist of 1 or
2 bytes, as selected by the DMACNTLn.TCS bit.
Note: 0000h is interpreted as 2
31
31
31
15
Reserved
Reserved
Reserved
Block Length Counter Register (BLTCn)
Device A Address Register (ADRAn)
Device B Address Counter Register (ADCBn)
Device B Address Register (ADRBn)
24
24
24
23
23
23
Block Length Counter
Device B Address Counter
Device A Address
Device B Address
16
-1 transfer cycles.
0
0
0
0