CP3UB26Y98NEPX National Semiconductor, CP3UB26Y98NEPX Datasheet - Page 24

• Manufacturer Part Number: CP3UB26Y98NEPX
• Manufacturer: National Semiconductor

Specifications of CP3UB26Y98NEPX

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Not Compliant

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6.0
The CP3UB26 supports a uniform 16M-byte linear address
space. Table 6 lists the types of memory and peripherals
that occupy this memory space. Unlisted address ranges
6.1
The operating environment controls whether external mem-
ory is supported and whether the reset vector jumps to a
code space intended to support In-System Programming
(ISP). Up to 12M of external memory space is available.
The operating mode of the device is controlled by the states
on the ENV[2:0] pins at reset and the states of the EMPTY
bits in the Protection Word, as shown in Table 7. Internal
pullups on the ENV[2:0] pins select IRE mode or ISP mode
if these pins are allowed to float.
When ENV[2:0] = 111b, IRE mode is selected unless the
EMPTY bits in the Protection word indicate that the program
flash memory is empty (unprogrammed), in which case ISP
mode is selected. When ENV[2:0] = 011b, ERE mode is se-
lected unless the EMPTY bits indicate that the program
flash memory is empty, in which case ISP mode is selected.
When ENV[2:0] = 110b, ISP mode is selected without re-
gard to the states of the EMPTY bits. See Section 8.4.2 for
more details.
In the DEV environment, the on-chip flash memory is dis-
abled, and the corresponding region of the address space
is mapped to external memory. DEVINT mode is equivalent
to DEV mode but maps static memory zone 0 to the on-chip
memory.
FF FB00h
FF FC00h
0D 0000h
0D 2000h
0E 0000h
0E 9200h
0E F000h
FF 0000h
FF F200h
FF F600h
00 0000h
04 0000h
40 0000h
80 0000h
Address
Start
Memory
OPERATING ENVIRONMENT
0C FFFFh
0D FFFFh
0E EFFFh
FE FFFFh
FF FBFFh
0D 1FFFh
0E 7FFFh
3F FFFFh
7F FFFFh
FF F1FFh
FF F5FFh
FF FAFFh
FF FFFFh
03 FFFFh
Address
End
Size in
3139K
4096K
8128K
Bytes
61952
23.5K
256K
576K
1280
56K
32K
256
8K
1K
1K
Table 6 CP3UB26 Memory Map
On-chip Flash Program Memory, including Boot
Memory
Reserved
On-chip Flash Data Memory
Reserved
System RAM
Reserved
CAN Buffers and Registers
External Memory Zone 1
External Memory Zone 2
Reserved
Peripherals and Other I/O Ports
BIU, DMA, Flash interfaces
I/O Expansion
Peripherals and Other I/O Ports
24
are reserved and must not be read or written. The BIU
zones are regions of the address space that share the same
control bits in the Bus Interface Unit (BIU).
Description
Static Zone 0
(mapped internally
in IRE and ERE
mode; mapped to
the external bus in
DEV mode)
N/A
Static Zone 1
Static Zone 2
N/A
IN/A
I/O Zone
N/A
BIU Zone