CP3UB26G18NEP National Semiconductor, CP3UB26G18NEP Datasheet - Page 57

• Manufacturer Part Number: CP3UB26G18NEP
• Manufacturer: National Semiconductor

Specifications of CP3UB26G18NEP

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Package Type: LQFP
• Lead Free Status / RoHS Status: Not Compliant

11.9.3
The PRSSC register is a byte-wide read/write register that
holds the clock divisor used to generate the Slow Clock from
the Main Clock. The register is initialized to B6h at reset.
SCDIV
11.9.4
The PRSAC register is a byte-wide read/write register that
holds the clock divisor values for prescalers used to gener-
ate the two auxiliary clocks from the Main Clock. The regis-
ter is initialized to FFh at reset.
ACDIV1
ACDIV2
7
7
Low Frequency Clock Prescaler Register
(PRSSC)
Auxiliary Clock Prescaler Register (PRSAC)
ACDIV2
low-frequency oscillator clock while the
MODE field is modified.
The Slow Clock Divisor field specifies a divi-
sor to be used when generating the Slow
Clock from the Main Clock. The Main Clock is
divided by a value of (2 × (SCDIV + 1)) to ob-
tain the Slow Clock. At reset, the SCDIV reg-
ister is initialized to B6h, which generates a
Slow Clock rate of 32786.885 Hz. This is
about 0.5% faster than a Slow Clock generat-
ed from an external 32768 Hz crystal network.
The Auxiliary Clock Divisor 1 field specifies
the divisor to be used for generating Auxiliary
Clock 1 from the Main Clock. The Main Clock
is divided by a value of (ACDIV1 + 1).
The Auxiliary Clock Divisor 2 field specifies
the divisor to be used for generating Auxiliary
Clock 2 from the Main Clock. The Main Clock
is divided by a value of (ACDIV2 + 1).
MODE2:0
000
001
010
011
100
101
110
111
4
SCDIV
Reserved
Reserved
Reserved
36 MHz
48 MHz
60 MHz
Reserved
Reserved
(from 12 MHz
input clock)
Frequency
3
Output
ACDIV2
Reserved
Reserved
Reserved
3× Mode
4× Mode
5× Mode
Reserved
Reserved
Description
0
0
57
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