CP3UB26G18NEP National Semiconductor, CP3UB26G18NEP Datasheet - Page 27

• Manufacturer Part Number: CP3UB26G18NEP
• Manufacturer: National Semiconductor

Specifications of CP3UB26G18NEP

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Package Type: LQFP
• Lead Free Status / RoHS Status: Not Compliant

IPRE
6.4.4
The SZCFG1 register is a word-wide, read/write register
that controls the timing and bus characteristics for off-chip
accesses selected with the SEL1 output signal.
At reset, the register is initialized to 069Fh. The register for-
mat is shown below.
WAIT
HOLD
RBE
WBR
BW
FRE
BW
15
7
WBR
Static Zone 1 Configuration Register (SZCFG1)
Reserved
6
The Preliminary Idle bit controls whether an
idle cycle is inserted prior to the current bus
cycle, when the new bus cycle accesses a dif-
ferent zone. No idle cycles are required for on-
chip accesses.
0
1
The Memory Wait field specifies the number
of TIW (internal wait state) clock cycles added
for each memory access, ranging from 000b
for no additional TIW wait cycles to 111b for
seven additional TIW wait cycles. These bits
are ignored if the SZCFG1.FRE bit is set.
The Memory Hold field specifies the number
of T hold clock cycles used for each memory
access, ranging from 00b for no T hold cycles
to 11b for three T hold clock cycles. These bits
are ignored if the SZCFG1.FRE bit is set.
The Read Burst Enable enables burst cycles
on 16-bit reads from 8-bit bus width regions of
the address space. This bit is ignored when
the
SZCFG1.BW is clear.
0
1
The Wait on Burst Read bit controls if a wait
state is added on burst read transaction. This
bit is ignored, when SZCFG1.FRE bit is set or
when SZCFG1.RBE is clear.
0
1
The Bus Width bit controls the bus width of the
zone.
0
1
The Fast Read Enable bit controls whether
fast read bus cycles are used. A fast read op-
eration takes one clock cycle. A normal read
operation takes at least two clock cycles.
0
1
–
–
–
–
–
–
–
–
–
–
RBE
No idle cycle (recommended).
Idle cycle inserted.
5
Burst read disabled.
Burst read enabled.
No TBW on burst read cycles.
One TBW on burst read cycles.
8-bit bus width.
16-bit bus width.
Normal read cycles.
Fast read cycles.
SZCFG1.FRE
12
4
HOLD
FRE
11
3
bit
IPRE IPST
10
2
is
WAIT
set
9
or
Res.
0
8
the
27
IPST
IPRE
6.4.5
The SZCFG2 register is a word-wide, read/write register
that controls the timing and bus characteristics for off-chip
accesses selected with the SEL2 output signal.
At reset, the register is initialized to 069Fh. The register for-
mat is shown below.
WAIT
HOLD
RBE
WBR
BW
BW
15
7
WBR
Static Zone 2 Configuration Register (SZCFG2)
Reserved
6
The Post Idle bit controls whether an idle cycle
follows the current bus cycle, when the next
bus cycle accesses a different zone.
0
1
The Preliminary Idle bit controls whether an
idle cycle is inserted prior to the current bus
cycle, when the new bus cycle accesses a dif-
ferent zone.
0
1
The Memory Wait field specifies the number
of TIW (internal wait state) clock cycles added
for each memory access, ranging from 000b
for no additional TIW wait cycles to 111b for
seven additional TIW wait cycles. These bits
are ignored if the SZCFG2.FRE bit is set.
The Memory Hold field specifies the number
of T hold clock cycles used for each memory
access, ranging from 00b for no T hold cycles
to 11b for three T hold clock cycles. These bits
are ignored if the SZCFG2.FRE bit is set.
The Read Burst Enable enables burst cycles
on 16-bit reads from 8-bit bus width regions of
the address space. This bit is ignored when
the
SZCFG2.BW is clear.
0
1
The Wait on Burst Read bit controls if a wait
state is added on burst read transaction. This
bit is ignored, when SZCFG2.FRE bit is set or
when SZCFG2.RBE is clear.
0
1
The Bus Width bit controls the bus width of the
zone.
0
1
–
–
–
–
–
–
–
–
–
–
RBE
No idle cycle.
Idle cycle inserted.
No idle cycle.
Idle cycle inserted.
5
Burst read disabled.
Burst read enabled.
No TBW on burst read cycles.
One TBW on burst read cycles.
8-bit bus width.
16-bit bus width.
SZCFG2.FRE
12
4
HOLD
FRE
11
3
bit
IPRE IPST
10
2
is
www.national.com
WAIT
set
9
or
Res.
0
8
the