CP3UB26G18NEP National Semiconductor, CP3UB26G18NEP Datasheet - Page 145

• Manufacturer Part Number: CP3UB26G18NEP
• Manufacturer: National Semiconductor

Specifications of CP3UB26G18NEP

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Package Type: LQFP
• Lead Free Status / RoHS Status: Not Compliant

19.6.6
The audio interface provides a FREEZE input, which allows
to freeze the status of the audio interface while a develop-
ment system examines the contents of the FIFOs and reg-
isters.
When the FREEZE input is asserted, the audio interface be-
haves as follows:
! The receive FIFO or receive DMA registers are not up-
! The receive status bits (RXO, RXE, RXF, and RXAF) are
! The transmit shift register (ATSR) is not updated with
! The transmit status bits (TXU, TXF, TXE, and TXAE) are
The time at which these registers are frozen will vary be-
cause they operate from a different clock than the one used
to generate the freeze signal.
dated with new data.
not changed, even though the receive FIFO or receive
DMA registers are read.
new data from the transmit FIFO or transmit DMA regis-
ters.
not changed, even though the transmit FIFO or transmit
DMA registers are written.
Freeze Mode
145
19.7
ADMACR
ARSCR
ARDR0
ARDR1
ARDR2
ARDR3
ATSCR
ATDR0
ATDR1
ATDR2
ATDR3
AISCR
AGCR
Name
ARFR
ACCR
ATFR
AUDIO INTERFACE REGISTERS
Table 64 Audio Interface Registers
FF FD4Ch
FF FD5Ch
FF FD4Ah
FF FD4Eh
FF FD50h
FF FD52h
FF FD54h
FF FD5Ah
FF FD5Eh
FF FD40h
FF FD42h
FF FD44h
FF FD46h
FF FD48h
FF FD56h
FF FD58h
Address
Configuration Register
Audio Interrupt Status
Audio Transmit Status
Audio Receive Status
Audio Transmit FIFO
and Control Register
and Control Register
and Control Register
Audio Transmit DMA
Audio Transmit DMA
Audio Transmit DMA
Audio Transmit DMA
Audio Receive FIFO
Audio Receive DMA
Audio Receive DMA
Audio Receive DMA
Audio Receive DMA
Audio Clock Control
Audio DMA Control
Audio Global
Description
Register 0
Register 1
Register 2
Register 3
Register 0
Register 1
Register 2
Register 3
Register
Register
Register
Register
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