CP3UB26G18NEP National Semiconductor, CP3UB26G18NEP Datasheet
CP3UB26G18NEP
Specifications of CP3UB26G18NEP
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CP3UB26G18NEP Summary of contents
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... Audio Microwiire/ GPIO Interface SPI TRI-STATE is a registered trademark of National Semiconductor Corporation. ©2007 National Semiconductor Corporation trade-off between battery size and operating time for hand- held and portable applications. In addition to providing the features needed for the next gen- eration of embedded products, the CP3UB26 is backed up ...
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General Description . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.0 Features . . . . . . . . ...
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Features CPU Features ! Fully static RISC processor core, capable of operating from MHz with zero wait/hold states ! Minimum 41.7 ns instruction cycle time with a 24-MHz in- ternal clock frequency, based on a 12-MHz ...
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Device Overview The CP3UB26 connectivity processor is a complete micro- computer with all system timing, interrupt logic, program memory, data memory, and I/O ports included on-chip, mak- ing it well-suited to a wide range of embedded applications. The block ...
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USB The CR16 USB node is a Universal Serial Bus (USB) Node controller compatible with USB Specification 1.1. It inte- grates the required USB transceiver, the Serial Interface En- gine (SIE), and USB endpoint FIFOs. A total of seven ...
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MICROWIRE/SPI The Microwire/SPI (MWSPI) interface module supports syn- chronous serial communications with other devices that conform to Microwire or Serial Peripheral Interface (SPI) specifications. It supports 8-bit and 16-bit data transfers. The Microwire interface allows several devices to communi- ...
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... National Semiconductor offers a complete and industry- proven application development environment for CP3UB26 Transaction applications, including the IAR Embedded Workbench, ...
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Signal Descriptions X1CKI/BBCLK 12 MHz Crystal or Ext. Clock X1CKO X2CKI 32.768 kHz Crystal X2CKO AVCC 1 AGND 1 ADVCC 1 Power ADGND CP3UB26 1 Supply VCC (LQFP-128) 6 GND 6 IOVCC 15 IOGND 14 Chip Reset RESET TMS ...
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Table 2 CP3UB26 LQFP-128 Signal Descriptions Name Pins I/O Primary Function Input 12 MHz Oscillator Input X1CKI 1 Output 12 MHz Oscillator Output X1CKO 1 Input 32 kHz Oscillator Input X2CKI 1 Output 32 kHz Oscillator Output X2CKO 1 Input ...
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Name Pins I/O 1 I/O ADC Input Channel 4 ADC4 1 I/O ADC Input Channel 5 ADC5 1 Input ADC Input Channel 6 ADC6 1 Input ADC Input Channel 7 ADC7 1 Input ADC Positive Voltage Reference VREFP 8 I/O ...
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Name Pins I/O Primary Function 1 I/O Generic I/O PG6 1 I/O Generic I/O PG7 1 I/O Generic I/O PH0 1 I/O Generic I/O PH1 1 I/O Generic I/O PH2 1 I/O Generic I/O PH3 1 I/O Generic I/O PH4 ...
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Table 3 CP3UB26 LQFP-144 Signal Descriptions Name Pins I/O Input 12 MHz Oscillator Input X1CKI 1 Output 12 MHz Oscillator Output X1CKO 1 Input 32 kHz Oscillator Input X2CKI 1 Output 32 kHz Oscillator Output X2CKO 1 Input Chip general ...
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Name Pins I/O Primary Function 1 I/O ADC Input Channel 4 ADC4 1 I/O ADC Input Channel 5 ADC5 1 Input ADC Input Channel 6 ADC6 1 Input ADC Input Channel 7 ADC7 1 Input ADC Positive Voltage Reference VREFP ...
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Name Pins I/O 1 I/O Generic I/O PF7 1 I/O Generic I/O PG0 1 I/O Generic I/O PG1 1 I/O Generic I/O PG2 1 I/O Generic I/O PG3 PG4 1 I/O Generic I/O PG5 1 I/O Generic I/O PG6 1 ...
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CPU Architecture The CP3UB26 uses the CR16C third-generation 16-bit CompactRISC processor core. The CPU implements a Re- duced Instruction Set Computer (RISC) architecture that al- lows an effective execution rate one instruction per clock cycle. For ...
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Interrupt Base Register (INTBASE) The INTBASE register holds the address of the dispatch ta- ble for exceptions. The dispatch table can be located any- where in the CPU address space. When loading the INTBASE register, bits ...
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CONFIGURATION REGISTER (CFG) The CFG register is used to enable or disable various oper- ating modes and to control optional on-chip caches. Be- cause the CP3UB26 does not have cache memory, the cache control bits in the CFG register ...
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ADDRESSING MODES The CR16C CPU core implements a load/store architec- ture, in which arithmetic and logical instructions operate on register operands. Memory operands are made accessible in registers using load and store instructions. For efficient implementation of I/O-intensive embedded ...
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STACKS A stack is a last-in, first-out data structure for dynamic stor- age of data and addresses. A stack consists of a block of memory used to hold the data and a pointer to the top of the stack. ...
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Mnemonic MOVi Rsrc/imm, Rdest MOVXB Rsrc, Rdest MOVZB Rsrc, Rdest MOVXW Rsrc, RPdest MOVZW Rsrc, RPdest MOVD imm, RPdest RPsrc, RPdest ADD[U]i Rsrc/imm, Rdest ADDCi Rsrc/imm, Rdest ADDD RPsrc/imm, RPdest MACQWa Rsrc1, Rsrc2, RPdest MACSWa Rsrc1, Rsrc2, RPdest MACUWa Rsrc1, ...
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Mnemonic Operands ASHUD Rsrc/imm, RPdest LSHi Rsrc/imm, Rdest LSHD Rsrc/imm, RPdest SBITi Iposition, disp(Rbase) Iposition, disp(RPbase) Iposition, (Rindex)disp(RPbasex) Iposition, abs Iposition, (Rindex)abs CBITi Iposition, disp(Rbase) Iposition, disp(RPbase) Iposition, (Rindex)disp(RPbasex) Iposition, abs Iposition, (Rindex)abs TBIT Rposition/imm, Rsrc TBITi Iposition, disp(Rbase) Iposition, ...
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Mnemonic RETX PUSH imm, Rsrc, RA POP imm, Rdest, RA POPRET imm, Rdest, RA LOADi disp(Rbase), Rdest abs, Rdest (Rindex)abs, Rdest (Rindex)disp(RPbasex), Rdest disp(RPbase), Rdest LOADD disp(Rbase), Rdest abs, Rdest (Rindex)abs, Rdest (Rindex)disp(RPbasex), Rdest disp(RPbase), Rdest STORi Rsrc, disp(Rbase) Rsrc, ...
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Mnemonic Operands STORMP imm3 DI EI EIWAIT NOP WAIT Table 5 Instruction Set Summary Store registers (R2-R5, R8-R11) to memory starting at (R7,R6) Disable maskable interrupts Enable maskable interrupts Enable maskable interrupts and wait for interrupt No ...
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Memory The CP3UB26 supports a uniform 16M-byte linear address space. Table 6 lists the types of memory and peripherals that occupy this memory space. Unlisted address ranges Start End Address Address 00 0000h 03 FFFFh 04 0000h 0C FFFFh ...
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Table 7 Operating Environment Selection ENV[2:0] EMPTY Operating Environment 111 No Internal ROM enabled (IRE) mode 011 No External ROM enabled (ERE) mode 000 N/A Development (DEV) mode Development (DEVINT) mode with 001 N/A internal memory 110 N/A In-System-Programming (ISP) ...
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I/O Zone Configuration Register (IOCFG) The IOCFG register is a word-wide, read/write register that controls the timing and bus characteristics of accesses to the 256-byte I/O Zone memory space (FF FB00h to FF FBFFh). The registers associated with Port ...
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IPRE The Preliminary Idle bit controls whether an idle cycle is inserted prior to the current bus cycle, when the new bus cycle accesses a dif- ferent zone. No idle cycles are required for on- chip accesses. – ...
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FRE The Fast Read Enable bit controls whether fast read bus cycles are used. A fast read op- eration takes one clock cycle. A normal read operation takes at least two clock cycles. – 0 Normal read cycles. – 1 ...
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System Configuration Registers The system configuration registers control and provide sta- tus for certain aspects of device setup and operation, such as indicating the states sampled from the ENV[2:0] inputs. The system configuration registers are listed in Table 9. ...
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MODULE STATUS REGISTER (MSTAT) The MSTAT register is a byte-wide, read-only register that indicates the general status of the device. The MCFG regis- ter format is shown below ISPRST WDRST Res. DPGMBUSY PGMBUSY OENV2:0 OENV2:0 ...
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Flash Memory The flash memory consists of the flash program memory and the flash data memory. The flash program memory is further divided into the Boot Area and the Code Area. A special protection scheme is applied to the ...
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Main Block 0 and 1 Main Block 0 and Main Block 1 hold the 256K-byte program space, which consists of the Boot Area and Code Area. Each block consists of sixteen 8K-byte sections. Write ac- cess by the CPU ...
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Main Block Page Erase A flash erase operation sets all of the bits in the erased re- gion. Pages of a main block can be individually erased if their write enable bits are set. This method cannot be used ...
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INFORMATION BLOCK WORDS Two words in the information blocks are dedicated to hold settings that affect the operation of the system: the Function Word in Information Block 0 and the Protection Word in In- formation Block 1. 8.4.1 Function ...
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Table 15 CPU Reset Behavior EMPTY ISPE Boot Area Not Empty ISP Defined Not Not Empty ISP Defined Not Empty No ISP Don’t Care Empty ISP Defined Not Empty ISP Defined Empty No ISP Don’t Care RDPROT The RDPROT field ...
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Flash Memory Information Block Address Register (FMIBAR/FSMIBAR) The FMIBAR register specifies the 8-bit address for read or write access to an information block. Because only word ac- cess to the information blocks is supported, the least signif- icant bit ...
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Flash Data Memory 0 Write Enable Register (FSM0WER) The FSM0WER register controls write protection for the flash data memory. The data block is divided into 16 512- byte sections. Each bit in the FSM0WER register controls write protection for ...
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Flash Memory Status Register (FMSTAT/ FSMSTAT) This register reports the currents status of the on-chip Flash memory. The FLSR register is clear after device reset. The CPU bus master has read/write access to this register ...
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Flash Memory Transition Time Reload Register (FMTRAN/FSMTRAN) The FMTRAN/FMSTRAN register is a byte-wide read/write register that controls some program/erase transition times. Software must not modify this register while program/erase operation is in progress (FMBUSY set). At reset, this regis- ...
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Flash Memory Recovery Time Reload Register (FMRCV/FSMRCV) The FMRCV/FSMRCV register is a byte-wide read/write register that controls the recovery delay time between two flash memory accesses. Software must not modify this reg- ister while a program/erase operation is in ...
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DMA Controller The DMA Controller (DMAC) has a register-based program- ming interface, as opposed to an interface based on I/O control blocks. After loading the registers with source and destination addresses, as well as block size and type of ...
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Direct mode supports two bus policies: intermittent and con- tinuous. In intermittent mode, the DMAC gives bus master- ship back to the CPU after every cycle. In continuous mode, the DMAC remains bus master until the transfer is complet- ed. ...
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If the DMASTAT.VLD bit is clear: 1. The transfer operation terminates. 2. The channel sets the DMASTAT.OVR bit. 3. The DMASTAT.CHAC bit is cleared interrupt is generated DMACNTLn.EOVR bit. The DMACNTLn.CHEN bit must be cleared before loading the ...
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Table 18 DMA Controller Registers Name Address ADCA2 FF F840h ADRA2 FF F844h ADCB2 FF F848h ADRB2 FF F84Ch BLTC2 FF F850h BLTR2 FF F854h DMACNTL2 FF F85Ch DMASTAT2 FF F85Eh ADCA3 FF F860h ADRA3 FF F864h ADCB3 FF F868h ...
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Block Length Register (BLTRn) The Block Length register is a 16-bit, read/write register. It holds the number of DMA transfers to be performed for the next block. Writing this register automatically sets the DM- ASTAT.VLD bit. 15 Block Length ...
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DMA Status Register (DMASTAT) The DMA status register is a byte-wide, read register that holds the status information for the DMA channel n. This register is cleared at reset. The reserved bits always return zero when read. The VLD, ...
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Interrupts The Interrupt Control Unit (ICU) receives interrupt requests from internal and external sources and generates interrupts to the CPU. Interrupts from the timers, UARTs, Microwire/ SPI interface, and Multi-Input Wake-Up module are all maskable interrupts. The highest-priority interrupt ...
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Interrupt Vector Register (IVCT) The IVCT register is a byte-wide read-only register which re- ports the encoded value of the highest priority maskable in- terrupt that is both asserted and enabled. The valid range is from 10h to 3Fh. ...
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Interrupt Enable and Mask Register 0 (IENAM0) The IENAM0 register is a word-wide read/write register which holds bits that individually enable and disable the maskable interrupt sources IRQ1 through IRQ15. The reg- ister is initialized to FFFFh at reset. ...
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MASKABLE INTERRUPT SOURCES Table 20 shows the interrupts assigned to various on-chip maskable interrupts. The priority of simultaneous maskable interrupts is linear, with IRQ47 having the highest priority. Table 20 Maskable Interrupts Assignment IRQ Number Description IRQ47 TWM (Timer ...
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Triple Clock and Reset The Triple Clock and Reset module generates a 12 MHz Main Clock and a 32.768 kHz Slow Clock from external crystal networks or external clock sources. It provides vari- ous clock signals for the rest ...
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EXTERNAL CRYSTAL NETWORK An external crystal network is connected to the X1CKI and X1CKO pins to generate the Main Clock, unless an external clock signal is driven on the X1CKI pin. A similar external crystal network may be used ...
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Table 22 Component Values of the Low Frequency Crystal Circuit Component Crystal Resonance Frequency Type Maximum Serial Resistance Maximum Shunt Capacitance Load Capacitance Min. Q factor Capacitor C1, C2 Capacitance Choose capacitor component values in the tables to obtain the ...
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SYSTEM CLOCK The System Clock drives most of the on-chip modules, in- cluding the CPU. Typically driven by the Main Clock, but it can also be driven by the PLL. In either case, the clock sig- nal ...
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Manual and SDI External Reset An external reset circuit based on the LM3724 5-Pin Micro- processor Reset Circuit is shown in Figure 9. The LM3724 produces a 190-ms logic low reset pulse when the power supply rises above a ...
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CLOCK AND RESET REGISTERS Table 23 lists the clock and reset registers. Table 23 Clock and Reset Registers Name Address CRCTRL FF FC40h PRSFC FF FC42h PRSSC FF FC44h PRSAC FF FC46h 11.9.1 Clock and Reset Control Register (CRCTRL) ...
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MODE field is modified. Output Frequency MODE2:0 (from 12 MHz input clock) 000 Reserved 001 Reserved 010 Reserved 011 36 MHz 100 48 MHz 101 60 MHz 110 Reserved 111 Reserved 11.9.3 Low Frequency Clock ...
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Power Management The Power Management Module (PMM) improves the effi- ciency of the CP3UB26 by changing the operating mode (and therefore the power consumption) according to the re- quired level of device activity. The device implements four power modes: ...
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IDLE MODE In Idle mode, the System Clock is disabled and therefore the clock is stopped to most modules of the device. The PLL and the high-frequency oscillator may be disabled as con- trolled by register bits. The low-frequency ...
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HALT The Halt Mode bit indicates whether the de- vice is in Halt mode. Before entering Halt mode, the WBPSM bit must be set. When the HALT bit is written with 1, the device enters the Halt mode at the ...
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Power Management Status Register (PMMSR) The Management Status Register (PMMR byte-wide, read/write register that provides status signals for the vari- ous clocks. The reset value of PMSR register bits de- pend on the status ...
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Entering Idle Mode Entry into Idle mode is performed by writing the PM- MCR.IDLE bit and then executing a WAIT instruction. The PMMCR.WBPSM bit must be set before the WAIT instruc- tion is executed. Idle mode ...
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Multi-Input Wake-Up The Multi-Input Wake-Up (MIWU) unit consists of two iden- tical 16-channel modules. Each module can assert a wake- up signal for exiting from a low-power mode, and each can assert an interrupt request on any of four ...
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Table 27 MIWU Sources MIWU Channel WUI0 WUI1 WUI2 WUI3 WUI4 WUI5 WUI6 WUI7 WUI8 WUI9 WUI10 WUI11 WUI12 WUI13 WUI14 WUI15 WUI16 WUI17 WUI18 WUI19 WUI20 WUI21 WUI22 WUI23 WUI24 WUI25 WUI26 WUI27 WUI28 WUI29 WUI30 WUI31 www.national.com 13.1 ...
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Wake-Up Edge Detection Register (WK0EDG) The WK0EDG register is a word-wide read/write register that controls the edge sensitivity of the MIWU channels. The WK0EDG register is cleared upon reset, which configures all channels to be triggered on rising edges. ...
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Wake-Up Interrupt Control Register 1 (WK0ICTL1) The WK0ICTL1 register is a word-wide read/write register that selects the interrupt request signal for the associated MIWU channels WUI7:0. At reset, the WK0ICTL1 register is cleared, which selects MIWU Interrupt Request 0 ...
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Wake-Up Pending Register (WK0PND) The WK0PND register is a word-wide read/write register in which the Multi-Input Wake-Up module latches any detect- ed trigger conditions. The CPU can only write any bit position in this register. If ...
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PROGRAMMING PROCEDURES To set up and use the Multi-Input Wake-Up function, use the following procedure. Performing the steps in the order shown will prevent false triggering of a wake-up condition. This same procedure should be used following a reset ...
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Input/Output Ports Each device has software-configurable I/O pins, or- ganized into 8-bit ports (not all bits are used in some ports). The ports are named Port B, Port C, Port E, Port F, Port G, Port ...
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Table 29 Port Registers Name Address PBALT FF FB00h PBDIR FF FB02h Port B Direction Register PBDIN FF FB04h Port B Data Input Register PBDOUT FF FB06h Port B Data Output Register Port B Weak Pull-Up PBWPU FF FB08h PBHDRV ...
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All of the port registers are byte-wide read/write registers, except for the port data input registers, which are read-only registers. Each register bit controls the function of the cor- responding port pin. For example, PGDIR.2 (bit 2 of the PGDIR ...
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Port High Drive Strength Register (PxHDRV) The PxHDRV register is a byte-wide, read/write register that controls the slew rate of the corresponding pins. The high drive strength function is enabled when the corresponding bits of the PxHDRV register are ...
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Analog to Digital Converter The integrated 12-bit ADC provides the following features: ! 8-input analog multiplexer ! 8 single-ended channels or 4 differential channels ! External filtering capability ! 12-bit resolution with 11-bit accuracy ! Sign bit + ...
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The output of the Input Multiplexer is available externally as the MUXOUT0 and MUXOUT1 signals. In single-ended mode, only MUXOUT0 is used. In differential mode, MUXOUT0 is the positive side and MUXOUT1 is the nega- tive side. The MUXOUT0 and ...
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TOUCHSCREEN INTERFACE The ADC provides an interface for 4-wire resistive touch- screens with the resolution necessary for applications such as signature analysis. A typical touchscreen configuration is shown in Figure 15. Figure 15. Touchscreen Interface A touchscreen consists of ...
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Measuring Pen Force Figure 17 shows equivalent circuits for the driver modes used to measure the X, Y, and Z coordinates, in which Z rep- resents pen force. In this discussion, the ohmic resistance of the drivers is neglected ...
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By extension, the ADC negative voltage reference can be internally connected to the TSY- terminal, to recover the full 4096 values. The Global Configuration Register (ADCGCR) provides the flexibility to implement any of these techniques. 15.3 ADC OPERATION IN ...
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ADC Global Configuration Register (ADCGCR) The ADCGCR register controls the basic operation of the in- terface. The CPU bus master has read/write access to the ADCGCR register. After reset this register is set to 0000h ...
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PREF_CFG The Positive Voltage Reference Configuration field specifies the source of the ADC positive voltage reference, according to the following table: PREF_CFG NREF_CFG The Negative Voltage Reference Configura- tion field specifies the source of the ADC ...
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ADC Conversion Control Register (ADCCNTRL) The ADCCNTRL register specifies the trigger conditions for an ADC conversion. 15 Reserved POL The ASYNC Polarity bit specifies the polarity of edges which trigger ADC conversions. 0 – ASYNC input is sensitive to ...
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ADC Result Register (ADCRESLT) The ADCRESLT register includes the software-visible end of a 4-word FIFO. Conversion results are loaded into the FIFO from the 12-bit ADC and unloaded when software reads the ADCRESLT register. The ADCRESLT register is read-only. ...
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Random Number Generator (RNG) The RNG unit is a hardware “true random” number genera- tor. When enabled, this unit provides up to 800 random bits per second. The bits are available for reading from a 16-bit register. The RNG ...
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RANDOM NUMBER GENERATOR REGISTER SET Table 31 lists the RNG registers. Table 34 RNG Registers Name Address RNGCST FF F280h RNGD FF F282h RNG Divisor Register RNGDIVH FF F284h RNG Divisor Register RNGDIVL FF F286h 16.2.1 RNG Control and ...
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USB Controller The CR16 USB node is an integrated USB node controller that features enhanced DMA support with many automatic data handling features compatible with USB specifica- tion versions 1.0 and 1.1. It integrates the required USB ...
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ENDPOINT OPERATION 17.2.1 Address Detection Packets are broadcast from the host controller to all nodes on the USB network. Address detection is implemented in hardware to allow selective reception of packets and to per- mit optimal use of CPU ...
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Bidirectional Control Endpoint FIFO0 Operation FIFO0 should be used for the bidirectional control endpoint 0. It can be configured to receive data sent to the default ad- dress with the DEF bit in the EPC0 register. Isochronous transfers are not ...
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Receive Endpoint FIFO Operation (RXFIFO1, RXFIFO2, RXFIFO3) The Receive FIFOs for endpoints 2, 4, and 6 support bulk, interrupt, and isochronous USB packet transfers larger than the actual FIFO size. If the packet length exceeds the FIFO size, software must ...
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Table 37 USB Controller Registers Name Address EPC0 FF FDC0h EPC1 FF FDD0h EPC2 FF FDD8h EPC3 FF FDE0h EPC4 FF FDDE8h EPC5 FF FDF0h EPC6 FF FDF8h TXS0 FF FDC4h TXS1 FF FDD4h TXS2 FF FDE4h TXS3 FF FDF4h ...
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NAT The Node Attached indicates that this node is ready to be detected as attached to USB. When clear, the transceiver forces SE0 on the USB node controller to prevent the hub (to which this node is connected) from detecting ...
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Main Event Register (MAEV) The Main Event Register summarizes and reports the main events of the USB transactions. This register provides read- only access. The MAEV register is clear after reset INTR RX_EV ULD ...
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SD3 The Suspend Detect 3 ms bit is set after IDLE have been detected on the upstream port, indicating that the device should be sus- pended. The suspend occurs under software control by writing the suspend value ...
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Receive Event Register (RXEV) The RXEV register reports the current status of the FIFO, used by the three Receive Endpoints. The RXEV register is clear after reset. It provides read-only access from the CPU bus RXOVRRN ...
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FIFO Warning Event Register (FWEV) The FWEV register signals whether a receive or transmit FIFO has reached its warning limit. It reports the status for all FIFOs, except for the Endpoint 0 FIFO warning limit can be ...
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MF The Missed SOF bit is set when the frame number in a valid received SOF does not match the expected next value, or when an SOF is not received within 12060 bit times. The MF bit provides read-only access. ...
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DTGL The DMA Toggle bit is used to determine the initial state of Automatic DMA (ADMA) opera- tions. Software initially sets this bit if starting with a DATA1 operation, and clears this bit if starting with a DATA0 operation. Writes ...
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DMA Mask Register (DMAMSK) Any set bit in the DMAMSK register enables automatic set- ting of the DMA bit in the ALTEV register when the respec- tive event in the DMAEV register occurs. Otherwise, setting the DMA bit is ...
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The erroneous packet is ignored and not transferred via DMA. If this bit is cleared, automatic error handling ceases. 17.3.24 Endpoint Control 0 Register (EPC0) The EPC0 register controls the mandatory Endpoint clear ...
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FLUSH Writing the Flush FIFO bit flushes all data from the control endpoint FIFOs, resets the endpoint to Idle state, clears the FIFO read and write pointer, and then clears itself. If the endpoint is currently using ...
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FLUSH Writing 1 to the Flush bit flushes all data from the control endpoint FIFOs, resets the end- point to Idle state, clears the FIFO read and write pointer, and then clears itself. If the end- point is currently using ...
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ACK_STAT The Acknowledge Status bit is valid when the TX_DONE bit is set. The meaning of the ACK_STAT bit differs depending on whether ISO or non-ISO operation is used (as selected by the ISO bit in the EPCn register). ! ...
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TFWL The Transmit FIFO Warning Limit bits specify how many more bytes can be transmitted from the respective FIFO before an underrun con- dition occurs. If the number of bytes remaining in the FIFO is equal to or less than ...
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Receive Command Register n (RXCn) Each of the receive endpoints (2, 4, and 6) has one RXCn register. The registers provide read/write access from the CPU bus. Reading reserved bits returns undefined data. Af- ter reset clear. ...
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CAN Module The CAN module contains a Full CAN class, CAN (Control- ler Area Network) serial bus interface for low/high speed ap- plications. It supports reception and transmission of extended frames with a 29-bit identifier, standard frames with an ...
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CAN CORE INTERFACE MANAGEMENT Interface Management Interface Management 18.2 BASIC CAN CONCEPTS This section provides a generic overview of the basic con- cepts of the Controller Area Network (CAN). The CAN protocol is a message-based protocol that allows 11 a ...
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The CAN protocol allows several transmitting modules to start a transmission at the same time as soon as they detect the bus is idle. During the start of transmission, every node monitors the bus line to detect whether its message ...
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Data Length Code (DLC) The DLC field indicates the number of bytes in the data field. It consists of four bits. The data field can be of length zero. The admissible number of data bytes for a data frame rang- ...
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A CAN data frame consists of the following fields: ! Start of Frame (SOF) ! Arbitration Field + Extended Arbitration ! Control Field ! Data Field ! Cyclic Redundancy Check Field (CRC) Arbitration Field 11 d IDENTIFIER 10 ... 0 ...
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Error Frame As shown in Figure 30, the Error Frame consists of the error flag and the error delimiter bit fields. The error flag field is built up from the various error flags of the different nodes. Therefore, its length ...
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ANY FRAME INT = Intermission Suspend Transmission is only for error passive nodes. 18.2.4 Error Types Bit Error A CAN device which is currently transmitting also monitors the bus. If the monitored bit value ...
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Error Active An error active unit can participate in bus communication and may send an active (“dominant”) error flag. Error Warning The Error Warning state is a sub-state of Error Active to in- dicate a heavily disturbed bus. The CAN ...
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Bit Time Logic In the Bit Time Logic (BTL), the CAN bus speed and the Synchronization Jump Width can be configured by software. The CAN module divides a nominal bit time into three time segments: synchronization segment, time segment ...
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Bus Signal CAN Clock PREVIOUS A BIT PREVIOUS A BIT Bus Signal CAN Clock PREVIOUS BIT PREVIOUS BIT 18.2.7 Clock Generator The CAN prescaler (PSC) is shown is Figure 37. It divides the CKI input clock by the value defined ...
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BASIC-CAN path. For reception of data frame or remote frames, the CAN module follows a “receive on first match” rule which means that a given message is only received ...
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With this lock function, software has the capability to save several messages with the same identifier or same identifier group into more than one buffer. For ex- ample, a buffer with the second highest priority will receive ...
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All contents of the hidden receive buffer are always copied into the respective receive buffer. This includes the received message ID as well as the received Data Length Code (DLC); therefore when some mask bits are set to don’t care, ...
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Read buffer Read CNSTAT Yes RX_READY? No Yes RX_BUSYx? No Interrupt Entry Point RX_OVERRUN? Write RX_READY Read buffer (id/data/control) Read CNSTAT Yes RX_BUSYx? No Yes RX_FULL or RX_OVERRUN? No Clear RX_PND Exit Figure 44. Buffer Read Routine (BUFFLOCK Disabled) The ...
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CNSTAT status section will be 0101b, as the buffer was RX_FULL (0100b) before. After finally reading the last re- ceived message, the CPU can reset the buffer to RX_READY. 18.6 TRANSMIT STRUCTURE To transmit a CAN message, software must configure ...
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TXPRI value and the 4-bit buffer number (0...14) as shown below. The lowest resulting num- ber results in the highest transmit priority TXPRI Table 44 shows the transmit priority configuration if ...
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TX Buffer States The transmission process can be started after software has loaded the buffer registers (data, ID, DLC, PRI) and set the buffer status from TX_NOT_ACTIVE to TX_ONCE, TX_RTR, or TX_ONCE_RTR. When the CPU writes TX_ONCE, the buffer ...
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Highest Priority Interrupt Code To reduce the decoding time for the CIPND register, the buffer interrupt request with the highest priority is placed as interrupt status code into the IST[3:0] section of the CSTP- ND register. Each of the ...
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MEMORY ORGANIZATION The CAN module occupies 144 words in the memory ad- dress space. This space is organized as 15 banks of 8 words per bank (plus one reserved bank) for the message buffers and 14 words (plus 2 ...
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CAN CONTROLLER REGISTERS Table 48 lists the CAN module registers. Table 48 CAN Controller Registers Name Address See CNSTAT Table 47. CGCR 0E F100h CTIM 0E F102h GMSKX 0E F104h GMSKB 0E F106h BMSKX 0E F108h BMSKB 0E F10Ah ...
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Table 49 Buffer Status Section of the CNSTAT Register ST3 (DIR) ST2 ST1 ...
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PRI The Transmit Priority Code field holds the software-defined transmit priority code for the message buffer. DLC The Data Length Code field determines the number of data bytes within a received/trans- mitted frame. For transmission, these bits need to be ...
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Storage of Messages with Less Than 8 Data Bytes The data bytes that are not used for data transfer are “don’t cares”. If the object is transmitted, the data within these bytes will be ignored. If the object is ...
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Storage of Remote Messages During remote frame transfer, the buffer registers DATA0– DATA3 are “don’t cares” remote frame is transmitted, the contents of these registers are ignored remote Buffer Address 15 14 Register 0E F0XEh ...
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CAN Global Configuration Register (CGCR) The CAN Global Configuration Register (CGCR 16-bit wide register used to: ! Enable/disable the CAN module. ! Configure the BUFFLOCK function for the message buff- er 0..14. ! Enable/disable the time stamp ...
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Sequence of Data Bytes on the Bus ID Data1 Storage of Data Bytes in the Buffer Memory Setting the DDIR bit will cause the direction of the data stor- age to be reversed — the last byte received is stored ...
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INTERNAL If the Internal function is enabled, the CANTX and CANRX pins of the CAN module are inter- nally connected to each other. This feature can be used in conjunction with the LOOP- BACK mode. This means that the CAN ...
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TSEG1 The Time Segment 1 field configures the length of the Time Segment 1 (TSEG1 not recommended to configure the time seg- ment smaller than 2 time quanta. (see Table 56). Table 56 Time Segment ...
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Basic Mask Register (BMSKB/BMSKX) The BMSKB and BMSKX registers allow masking the buffer 14, or “don’t care” the incoming extended/standard identifier bits, RTR/XRTR, and IDE. Throughout this document, the two 16-bit registers BMSKB and BMSKX are referenced to as ...
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CAN Interrupt Clear Register (CICLR) The CICLR register bits individually clear CAN interrupt pending flags caused by the message buffers and from the Error Management Logic. Do not modify this register with in- structions that access the register as ...
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CAN Error Counter Register (CANEC) The CANEC register reports the values of the CAN Receive Error Counter and the CAN Transmit Error Counter REC 0 R REC The CAN Receive Error Counter field reports the value ...
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DRIVE The Drive bit shows the output value on the CANTX pin at the time of the error. Note that a receiver will not drive the bus except during ACK and during an active error flag. 18.10.17 CAN Timer Register ...
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Table 62 CAN Module Internal Timing Cycle Task Count Copy hidden buffer to receive 17 message buffer Update status from TX_RTR 3 to TX_ONCE_RTR Schedule a message for 2 transmission The critical path derives from receiving a remote frame, which ...
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USAGE HINT Under certain conditions, the CAN module receives a frame sent by itself, even though the loopback feature is disabled. Two conditions must be true to cause this malfunction transmit buffer and at least one receive ...
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Advanced Audio Interface The Advanced Audio Interface (AAI) provides a serial syn- chronous, full duplex interface to codecs and similar serial devices. The transmit and receive paths may operate asyn- chronously with respect to each other. Each path uses ...
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Synchronous Mode In synchronous mode, the receive and transmit paths of the audio interface use the same shift clock and frame sync sig- nal. The bit shift clock and frame sync signal for both paths are derived from the ...
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On the receiver side, only the valid data bits which were re- ceived during the slots assigned to this interface are copied into the receive FIFO or DMA registers. The assignment of slots to the receiver is specified by the ...
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Figure 59. Accessing Three Devices in Network Mode 19.3 BIT CLOCK GENERATION An 8-bit prescaler is provided to divide the audio interface input clock down to the required bit clock rate. Software can choose between two input clock sources, a ...
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Figure 60 shows the interrupt structure of the AAI. RXIE RXIP = 1 RXEIE RXEIP = 1 TXIE TXIP = 1 TXEIE TXEIP = 1 Figure 60. AAI Interrupt Structure 19.5.3 Normal Mode In normal mode, each frame sync signal ...
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Network Mode In network mode, each frame sync signal marks the begin- ning of new frame. Each frame can consist four slots. The audio interface operates in a similar way to nor- mal mode, however, in ...
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If the corresponding Frame Sync Select (FSS) bit in the Au- dio Control and Status register is set, the receive and/or transmit path generates or recognizes long frame sync puls- es. For 8-bit data, the frame sync pulse generated will ...
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IOM-2 Mode The AAI can operate in a special IOM-2 compatible mode to allow to connect to an external ISDN controller device. In this IOM-2 mode, the AAI can only operate as a slave, i.e. the bit clock and ...
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Freeze Mode The audio interface provides a FREEZE input, which allows to freeze the status of the audio interface while a develop- ment system examines the contents of the FIFOs and reg- isters. When the FREEZE input is asserted, ...
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Audio Receive FIFO Register (ARFR) The Audio Receive FIFO register shows the receive FIFO location currently addressed by the Receive FIFO Read Pointer (RRP). The receive FIFO receives 8-bit or 16-bit data from the Audio Receive Shift Register (ARSR), ...
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Audio Global Configuration Register (AGCR) The AGCR register controls the basic operation of the inter- face. The CPU bus master has read/write access to the AGCR register. After reset, this register is clear IEBC ...
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IOM2 The IOM-2 Mode bit selects the normal PCM interface mode or a special IOM-2 mode used to connect to external ISDN controller devic- es. The AAI can only operate as a slave in the IOM-2 mode, i.e. the bit ...
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Audio Receive Status and Control Register (ARSCR) The ARSCR register is used to control the operation of the receiver path of the audio interface. It also holds bits which report the current status of the receive FIFO. The CPU ...
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Audio Transmit Status and Control Register (ATSCR) The ASCR register controls the basic operation of the inter- face. It also holds bits which report the current status of the audio communication. The CPU bus master has read/write access to ...
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Audio Clock Control Register (ACCR) The ACCR register is used to control the bit timing of the au- dio interface. After reset, this register is clear. 7 FCPRS 15 BCPRS CSS The Clock Source Select bit selects one out ...
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CVSD/PCM Conversion Module The CVSD/PCM module performs conversion between CVSD data and PCM data, in which the CVSD encoding is as defined in the Bluetooth specification and the PCM en- coding may be 8-bit µ-Law, 8-bit A-Law, or 13-bit ...
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If the module is only used for PCM conversions, the CVSD clock can be disabled by clearing the CVSD Clock Enable bit (CLKEN) in the control register. 20.3 CVSD CONVERSION The CVSD/PCM converter module transforms either 8-bit logarithmic or 13- ...
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The CVSD/PCM module only supports indirect DMA trans- fers. Therefore, transferring PCM data between the CVSD/ PCM module and another on-chip module requires two bus cycles. The trigger for DMA may also trigger an interrupt if the cor- responding enable ...
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Logarithmic PCM Data Input Register (LOGIN) The LOGIN register is an 8-bit wide write-only register used to receive 8-bit logarithmic PCM data from the periph- eral bus and convert it into 13-bit linear PCM data. 7 LOGIN ...
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DMAPI The DMA Enable for PCM In bit enables hard- ware DMA control for writing PCM data into the PCMIN register. If cleared, DMA support is disabled. After reset, this bit is clear. 0 – PCM input DMA disabled. 1 ...
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UART Modules The CP3UB26 provides four UART modules. Each UART module is a full-duplex Universal Asynchronous Receiver/ Transmitter that supports a wide range of software-pro- grammable baud rates and data formats. It handles auto- matic parity generation and several ...
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Data bits are sensed by taking a majority vote of three sam- ples latched near the midpoint of each baud (bit time). Nor- mally, the position of the samples within the baud is determined automatically, but software can override the ...
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Synchronous Mode The synchronous mode of the UART enables the device to communicate with other devices using three communication signals: transmit, receive, and clock. In this mode, data bits are transferred synchronously with the UART clock signal. Data bits ...
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Start 2 8-Bit Data Bit Start 2a 8-Bit Data Bit Start 2b 8-Bit Data Bit Start 2c 8-Bit Data Bit Figure 70. 8-Bit Data Frame Options Start 3 9-Bit Data Bit Start 3a 9-Bit Data Bit Figure 71. 9-bit Data ...
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UFE UDOE UPE ! ! UEEI UERR UERI URBF UETI UTBE UEFCI UDCTS Figure 72. UART Interrupts 21.2.8 DMA Support 21.2.9 Break Generation and Detection 21.2.10 Parity Generation and Detection RX Interrupt TX Interrupt FC Interrupt DS066 ...
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UART REGISTERS Table 67 UART Registers Name Address Table 67 UART Registers Name Description Address Description ...
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Table 67 UART Registers Name Address 21.3.1 UART Receive Data Buffer (UnRBUF) 21.3.2 UART Transmit Data Buffer (UnTBUF) 21.3.3 UART Baud Rate Prescaler (UnPSR) 21.3.4 UART Baud Rate Divisor (UnBAUD) Description 21.3.5 UART Frame Select Register (UnFRS) ...
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UART Mode Select Register 1 (UnMDSL1) 21.3.7 UART Status Register (UnSTAT) ...
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UART Interrupt Control Register (UnICTRL) 21.3.9 UART Oversample Rate Register (UnOVR) UOVSR3:0 Oversampling Rate ...
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UART Mode Select Register 2 (UnMDSL2) 21.3.11 UART Sample Position Register (UnSPOS) Oversampling Rate 21.4 BAUD RATE CALCULATIONS 21.4.1 Asynchronous Mode Sample Position ----------------------------- - ------------------------------ - = = ----------------- - = ...
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Synchronous Mode = ---------------------------- - SYS_CLK = 48 MHz Baud Rate %err Table 68 Baud Rate Programming SYS_CLK = 24 MHz SYS_CLK = 12 MHz %err O N SYS_CLK = 10 MHz P ...
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SYS_CLK = 8 MHz Baud Rate %err SYS_CLK = 3 MHz Baud Rate %err Table 69 Baud Rate Programming SYS_CLK = 6 MHz SYS_CLK = 5 MHz %err O N SYS_CLK ...
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Microwire/SPI Interface Master 22.1 MICROWIRE OPERATION ! ! ! ! ! ! ! ! ! ! ! ! Figure 73. Microwire Interface 22.1.1 Shifting Slave ...
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Interrupt Request Write Data Write Data System Clock 22.1.2 Reading 22.1.3 Writing Control + Status 16-BIt Read Buffer MWDAT 8 8 Slave 16-BIt Shift Register Data Out Master Slave Data In Master MSK Clock Prescaler + Select Master Figure 74. ...
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MASTER MODE MSK Shift Out MSB Data Out Sample Point Data In MSB MSK Shift Out MSB Data Out Sample Point MSB Data In MSK Shift Out Data Out MSB Sample Point Data In MSB MSK Shift Out Data ...
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SLAVE MODE 22.4 INTERRUPT GENERATION Table 70 Microwire Interrupt Trigger Condition Interrupt Status Enable Bit Bit in the Condition in the MWSTAT MWCTRL1 Register Register Figure 79. MWSPI Interrupts Description ...
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MICROWIRE INTERFACE REGISTERS Table 71 Microwire Interface Registers Name Address 22.5.1 Microwire Data Register (MWDAT) Figure 80. MWDAT Register 22.5.2 MICROWIRE Control Register (MWCTL1) Description Pin State When Disabled ...
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Microwire Status Register (MWSTAT) ...
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ACCESS.bus Interface ! ! ! ! 23.1 ACB PROTOCOL OVERVIEW 23.1.1 Data Transactions SDA SCL Data Line Change Stable: of Data Data Valid Allowed Figure 81. Bit Transfer Start and Stop SDA SCL S Start Condition Figure 82. Start ...
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Acknowledge Cycle Acknowledgment Signal from Receiver SDA MSB SCL ACK Start Condition Byte Complete Interrupt Within Receiver Figure 83. ACCESS.bus Data Transaction Data Output by Transmitter Data Output by Receiver 3 ...
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ACB FUNCTIONAL DESCRIPTION 23.2.1 Master Mode Sending the Address Byte Master Transmit Master Receive Master Stop ...
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Master Bus Stall ! ! ! Repeated Start Master Error Detections Bus Idle Error Recovery 23.2.2 Slave Mode ! ! ! Slave Receive and Transmit Slave Bus Stall Slave Error Detections ...
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Power Down 23.2.3 SDA and SCL Pins Configuration 23.2.4 ACB Clock Frequency Configuration 23.3 ACCESS.BUS INTERFACE REGISTERS Table 72 ACCESS.bus Interface Registers Name Address 23.3.1 ACB Serial Data Register (ACBSDA) 23.3.2 ACB Status Register (ACBST) Description ...
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ACB Control Status Register (ACBCST ...
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ACB Control Register 1 (ACBCTL1) ...
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ACB Control Register 2 (ACBCTL2) 23.3.6 ACB Control Register 3 (ACBCTL3) ...
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ACB Own Address Register 1 (ACBADDR1) 23.3.8 ACB Own Address Register 2 (ACBADDR2) 23.4 USAGE HINTS ! ! ! ! ...
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Avoiding Bus Error During Write Transaction /*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% ; NAME: ACBRead Reads "Count" byte(s) from selected I2C Slave. ; Read or Write operation (as recorded in NextAddress), a "dummy" write transaction is ; initiated to reset the address to the ...
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ACBSTOP; return (ACB_NOERR); } /*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% ; NAME: ACBStartX Initiates an ACB bus transaction by sending the Start bit, followed by the Slave address ; and R/W flag PARAMETERS: UBYTE Slave - ; UBYTE R_nW - ; ...
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Timing and Watchdog Module 24.1 TWM STRUCTURE REAL TIME TIMER (T0) Slow Clock WATCHDOG Figure 86. Timing and Watchdog Module Block Diagram 24.2 TIMER T0 OPERATION ---------------------------------------------------------------------- - T0IN 5-Bit Prescaler Counter (TWCP) TWW/MT0 Register T0CSR Contrl. Reg. Restart ...
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WATCHDOG OPERATION ! ! ! 24.3.1 Register Locking 24.3.2 Power Save Mode Operation Note: 24.4 TWM REGISTERS Table 73 TWM Registers Name Address Description ...
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Timer and Watchdog Configuration Register (TWCFG) 24.4.2 Timer and Watchdog Clock Prescaler Register (TWCP) Clock Divisor MDIV (f = 32.768 kHz) SCLK 24.4.3 TWM Timer 0 Register (TWMT0) T0IN Frequency ...
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TWMT0 Control and Status Register (T0CSR) 24.4.5 Watchdog Count Register (WDCNT) 24.4.6 Watchdog Service Data Match Register (WDSDM) 24.5 WATCHDOG PROGRAMMING PROCEDURE ...
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Multi-Function Timer ! ! ! Clock Source System Clock Figure 87. Multi-Function Timer Block Diagram 25.1.1 Timer/Counter Block ! ! ! ! Prescaler Register TPRSC Reset 5-Bit System Prescaler Counter Clock TB Synchr. Figure 88. Multi-Function Timer Clock Source ...
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Counter Clock Source Select ! ! ! ! ! Prescaler Prescaler Output TB Counter Clock Slow Clock Limitations in Low-Power Modes External Event Clock Pulse Accumulate Mode Figure 89. Pulse-Accumulate Mode 25.2 TIMER OPERATING MODES ! ! ! ! DS083 ...
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Mode 1: Processor-Independent PWM Timer 1 Clock Timer 2 Clock Clock Selector Figure 90. Processor-Independent PWM Mode Reload A = Time 1 TAPND TCRA Underflow TAIEN Timer/Counter 1 TCNT1 TAEN Underflow TBIEN Reload B = Time 2 TBPND TCRB ...
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Mode 2: Dual Input Capture Timer 1 Clock Timer 2 Clock TAPND Capture A TCRA Preset TAEN TCPND Timer/Counter 1 TCNT1 Underflow Preset TBEN Capture B TCRB TBPND TDPND Timer/Counter 2 TnCNT2 Underflow Figure 91. Dual-Input Capture Mode Timer ...
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Mode 3: Dual Independent Timer/Counter Timer 1 Clock Timer 2 Clock Clock Selector Figure 92. Dual-Independent Timer/Counter Mode Reload A TAPND TCRA Underflow TAIEN Timer/Counter 1 TCNT1 TAEN Reload B TCRB Underflow TDIEN Timer/Counter 2 TDPND TCNT2 Timer Interrupt ...
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Mode 4: Input Capture Plus Timer Timer 1 Clock Timer 2 Clock Reload A TCRA Underflow Timer/Counter 1 TCNT1 Capture B TCRB Preset TBEN Timer/Counter 2 TnCNT2 Figure 93. Input Capture Plus Timer Mode TAPND Timer Interrupt 1 TAIEN ...
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TIMER INTERRUPTS Mode 1 Interrupt Sys. Int. Pending PWM + Counter Bit Mode 1 TAEN I/O TBEN PWM + Counter 25.4 TIMER I/O FUNCTIONS Table 74 Timer Interrupts Overview Mode 2 Dual Input Capture + Counter Table 75 Timer ...
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TIMER REGISTERS Table 76 Multi-Function Timer Registers Name Address 25.5.1 Clock Prescaler Register (TPRSC) 25.5.2 Clock Unit Control Register (TCKC) Description 25.5.3 Timer/Counter 1 Register (TCNT1) 25.5.4 Timer/Counter 2 Register (TCNT2) ...
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Reload/Capture A Register (TCRA) 25.5.6 Reload/Capture B Register (TCRB) 25.5.7 Timer Mode Control Register (TCTRL) ...
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Timer Interrupt Control Register (TICTL) 25.5.9 Timer Interrupt Clear Register (TICLR) ...
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Versatile Timer Unit (VTU MODE Timer Subsystem PRSC = = Prescaler Counter Count1 - Compare Capture PERCAP1 - Compare Capture DTYCAP1 I/O Control I/O Control TIO1 TIO2 Figure ...