ISP1183BS STEricsson, ISP1183BS Datasheet - Page 40

• Manufacturer Part Number: ISP1183BS
• Manufacturer: STEricsson

Specifications of ISP1183BS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 41.
[1]
ISP1183_3
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Reset value undefined after a bus reset.
[1]
Frame Number register: bit allocation
12.4.3 Frame Number register (R: B4h)
12.4.4 Chip ID register (R: B5h)
15
R
0
R
7
0
Table 40.
This command returns the frame number of the last successfully received SOF. It is
followed by reading one or two bytes from the Frame Number register, containing the
frame number (lower byte first). The Frame Number register is shown in
Remark: After a bus reset, the value of the Frame Number register is undefined.
Code: B4h — read frame number
Transaction — read 1 byte or 2 bytes
Table 42.
Table 43.
This command reads the chip identification code and hardware version number. Firmware
must check this information to determine supported functions and features. This
command accesses the Chip ID register, which is shown in
Code: B5h — read chip ID
Transaction — read 2 bytes
Bit
15 to 0
Bit
15 to 11
10 to 8
7 to 0
A0
HIGH
LOW
LOW
14
R
0
R
6
0
Symbol
UNLOCK[15:0] Sending data AA37h unlocks internal registers and FIFOs for writing,
Phase
command
data
data
Lock register: bit description
Frame Number register: bit description
Example of Frame Number register access
Symbol
-
SOFRH[2:0]
SOFRL[7:0]
reserved
13
R
0
R
5
0
Rev. 03 — 20 January 2009
Bus lines
D[7:0]
D[7:0]
D[7:0]
Description
following a resume.
Description
reserved
SOF frame number (upper byte)
SOF frame number (lower byte)
12
R
0
R
4
0
SOFRL[7:0]
Low-power USB Peripheral Controller with DMA
Byte #
-
0
1
11
R
0
R
3
0
Description
command code (B4h)
frame number (lower byte)
frame number (upper byte)
10
R
0
R
2
0
Table
SOFRH[2:0]
44.
© ST-NXP Wireless 2009. All rights reserved.
R
9
0
R
1
0
ISP1183
Table
41.
R
8
0
R
0
0
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