ISP1183BS STEricsson, ISP1183BS Datasheet - Page 14

• Manufacturer Part Number: ISP1183BS
• Manufacturer: STEricsson

Specifications of ISP1183BS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

9. Endpoint description
Table 4.
[1]
[2]
ISP1183_3
Product data sheet
Endpoint
identifier
0
0
1 to 14
The total amount of FIFO storage allocated to enabled endpoints must not exceed 2462 bytes.
IN: input for the USB host (ISP1183 transmits); OUT: output from the USB host (ISP1183 receives). The data flow direction is
determined by bit EPDIR in the Endpoint Configuration register.
Endpoint access and programmability
FIFO size (bytes)
64 (fixed)
64 (fixed)
programmable
9.1 Endpoint access
9.2 Endpoint FIFO size
Each USB device is logically composed of several independent endpoints. An endpoint
acts as a terminus of a communication flow between the host and the device. At design
time, each endpoint is assigned a unique number (endpoint identifier, see
combination of the device address (given by the host during enumeration), the endpoint
number, and the transfer direction allows each endpoint to be uniquely referenced.
The ISP1183 has 16 endpoints: endpoint 0 (control IN and OUT) plus 14 configurable
endpoints, which can individually be defined as interrupt, bulk or isochronous: IN or OUT.
Each enabled endpoint has an associated FIFO, which can be accessed either using the
PIO or DMA interface.
Table 4
access. Endpoints 1 to 14 also support DMA access. FIFO DMA access is selected and
enabled through bits EPDIX[3:0] of the DMA Configuration register and bit DMAEN of the
DMA Function and Scratch register. A detailed description of the DMA operation is given
in
The FIFO size determines the maximum packet size that the hardware can support for a
given endpoint. Only enabled endpoints are allocated space in the shared FIFO storage,
disabled endpoints have zero bytes.
The following bits in the Endpoint Configuration Register (ECR) affect FIFO allocation:
Remark: Register changes that affect the allocation of the shared FIFO storage among
endpoints must not be made while valid data is present in any FIFO of enabled endpoints.
Such changes will render all FIFO contents undefined.
•
•
•
Section
Endpoint enable bit (FIFOEN)
Size bits of an enabled endpoint (FFOSZ[3:0])
Isochronous bit of an enabled endpoint (FFOISO)
lists endpoint access modes and programmability. All endpoints support I/O mode
[1]
10.
Double buffering I/O mode
no
no
supported
Rev. 03 — 20 January 2009
access
yes
yes
supported
Table 5
Low-power USB Peripheral Controller with DMA
lists programmable FIFO sizes.
DMA mode
access
no
no
supported
© ST-NXP Wireless 2009. All rights reserved.
Endpoint type
control OUT
control IN
programmable
ISP1183
Table
[2]
[2]
4). The
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