ISP1183BS STEricsson, ISP1183BS Datasheet - Page 18

• Manufacturer Part Number: ISP1183BS
• Manufacturer: STEricsson

Specifications of ISP1183BS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ISP1183_3
Product data sheet
10.2 8237 compatible mode
8237 compatible DMA mode is selected by clearing bit DAKOLY in the Hardware
Configuration register (see
Table
Table 8.
The DMA subsystem of an IBM-compatible PC is based on the Intel 8237 DMA controller.
It operates as a ‘fly-by’ DMA controller: data is not stored in the DMA controller, but it is
transferred between an I/O port and a memory address. A typical example of the ISP1183
in 8237-compatible DMA mode is given in
The 8237 has two control signals for each DMA channel: DREQ (DMA request) and
DACK_N (DMA acknowledge). General control signals are HRQ (hold request) and HLDA
(hold acknowledge). The bus operation is controlled using MEMR_N (memory read),
MEMW_N (memory write), IOR_N (I/O read) and IOW_N (I/O write).
The following example shows the steps that occur in a typical DMA transfer:
Symbol
DREQ
DACK
RD_N
WR_N
1. The ISP1183 receives a data packet in one of its endpoint FIFOs. The packet must be
2. The ISP1183 asserts the DREQ signal requesting the 8237 for a DMA transfer.
3. The 8237 asks the CPU to release the bus by asserting the HRQ signal.
4. After completing the current instruction cycle, CPU places bus control signals
5. The 8237 sets its address lines to 1234h and activates the MEMW_N and IOR_N
6. The 8237 asserts DACK_N to inform the ISP1183 that it will start a DMA transfer.
Fig 9. ISP1183 in 8237-compatible DMA mode
transferred to memory address 1234h.
(MEMR_N, MEMW_N, IOR_N and IOW_N) and address lines in 3-state and asserts
HLDA to inform the 8237 that it has control of the bus.
control signals.
8.
8237 compatible mode: pin functions
Description
DMA request
DMA acknowledge
read strobe
write strobe
ISP1183
DATA[7:0]
WR_N
DREQ
DACK
RD_N
Rev. 03 — 20 January 2009
Table
20). The pin functions for this mode are shown in
I/O
O
I
I
I
RAM
Low-power USB Peripheral Controller with DMA
Figure
Function
instructs the ISP1183 to put data on the bus
instructs the ISP1183 to get data from the bus
ISP1183 requests a DMA transfer
DMA controller confirms the transfer
MEMR_N
MEMW_N
DREQ
DACK_N
IOR_N
IOW_N
CONTROLLER
9.
DMA
8237
HLDA
HRQ
© ST-NXP Wireless 2009. All rights reserved.
HRQ
HLDA
004aaa291
CPU
ISP1183
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