PSD834F2-15J STMicroelectronics, PSD834F2-15J Datasheet - Page 46

• Manufacturer Part Number: PSD834F2-15J
• Manufacturer: STMicroelectronics

Specifications of PSD834F2-15J

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: PLCC
• Mounting: Surface Mount
• Pin Count: 52
• Lead Free Status / RoHS Status: Compliant

PSD834F2V
I/O PORTS
There are four programmable I/O ports: Ports A, B,
C, and D. Each of the ports is eight bits except Port
D, which is 3 bits. Each port pin is individually user
configurable, thus allowing multiple functions per
port. The ports are configured using PSDsoft Ex-
press Configuration or by the MCU writing to on-
chip registers in the CSIOP space.
The topics discussed in this section are:
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■
■
■
■
General Port Architecture
The general architecture of the I/O Port block is
shown in Figure 22. Individual Port architectures
are shown in Figure 24 to Figure 27. In general,
once the purpose for a port pin has been defined,
Figure 22. General I/O Port Architecture
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General Port architecture
Port operating modes
Port Configuration Registers (PCR)
Port Data Registers
Individual Port functionality.
ADDRESS
ALE
MACROCELL OUTPUTS
EXT CS
WR
ENABLE PRODUCT TERM ( .OE )
WR
WR
CONTROL REG.
CPLD-INPUT
DATA OUT
READ MUX
DIR REG.
D
D
G
D
D
REG.
D
B
P
Q
Q
Q
Q
DATA IN
DATA OUT
ADDRESS
that pin is no longer available for other purposes.
Exceptions are noted.
As shown in Figure 22, the ports contain an output
multiplexer whose select signals are driven by the
configuration bits in the Control Registers (Ports A
and B only) and PSDsoft Express Configuration.
Inputs to the multiplexer include the following:
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■
■
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The Port Data Buffer (PDB) is a tri-state buffer that
allows only one source at a time to be read. The
Port Data Buffer (PDB) is connected to the Internal
Data Bus for feedback and can be read by the
MCU. The Data Out and macrocell outputs, Direc-
tion and Control Registers, and port pin input are
all connected to the Port Data Buffer (PDB).
Output data from the Data Out register
Latched address outputs
CPLD macrocell output
External Chip Select (ECS0-ECS2) from the
CPLD.
OUTPUT
SELECT
OUTPUT
MUX
ENABLE OUT
MACROCELL
INPUT
PORT PIN
AI02885